cputable.c

来自「Linux Kernel 2.6.9 for OMAP1710」· C语言 代码 · 共 631 行 · 第 1/2 页

    	0xffffffff, 0x80010200, "7455",
	CPU_FTR_COMMON |
    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
	CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
	CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
	CPU_FTR_L3_DISABLE_NAP | CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
	COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
	32, 32,
	__setup_cpu_745x
    },
    {	/* 7455 others */
    	0xffff0000, 0x80010000, "7455",
	CPU_FTR_COMMON |
    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
	CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
	CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
	CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
	COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
	32, 32,
	__setup_cpu_745x
    },
    {	/* 7447/7457 Rev 1.0 */
    	0xffffffff, 0x80020100, "7447/7457",
	CPU_FTR_COMMON |
    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
	CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
	CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
	CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
	COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
	32, 32,
	__setup_cpu_745x
    },
    {	/* 7447/7457 Rev 1.1 */
    	0xffffffff, 0x80020101, "7447/7457",
	CPU_FTR_COMMON |
    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
	CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
	CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
	CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
	COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
	32, 32,
	__setup_cpu_745x
    },
    {	/* 7447/7457 Rev 1.2 and later */
    	0xffff0000, 0x80020000, "7447/7457",
	CPU_FTR_COMMON |
    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
	CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
	CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
	CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
	COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
	32, 32,
	__setup_cpu_745x
    },
    {	/* 7447A */
    	0xffff0000, 0x80030000, "7447A",
	CPU_FTR_COMMON |
    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
	CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
	CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
	CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
	COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
	32, 32,
	__setup_cpu_745x
    },
    {	/* 82xx (8240, 8245, 8260 are all 603e cores) */
	0x7fff0000, 0x00810000, "82xx",
	CPU_FTR_COMMON |
	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB,
	COMMON_PPC,
	32, 32,
	__setup_cpu_603
    },
    {	/* All G2_LE (603e core, plus some) have the same pvr */
	0x7fff0000, 0x00820000, "G2_LE",
	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
	CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
	COMMON_PPC,
	32, 32,
	__setup_cpu_603
    },
    {	/* default match, we assume split I/D cache & TB (non-601)... */
    	0x00000000, 0x00000000, "(generic PPC)",
	CPU_FTR_COMMON |
    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
	COMMON_PPC,
	32, 32,
	__setup_cpu_generic
    },
#endif /* CLASSIC_PPC */
#ifdef CONFIG_PPC64BRIDGE
    {	/* Power3 */
    	0xffff0000, 0x00400000, "Power3 (630)",
	CPU_FTR_COMMON |
    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
    	COMMON_PPC | PPC_FEATURE_64,
	128, 128,
	__setup_cpu_power3
    },
    {	/* Power3+ */
    	0xffff0000, 0x00410000, "Power3 (630+)",
	CPU_FTR_COMMON |
    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
    	COMMON_PPC | PPC_FEATURE_64,
	128, 128,
	__setup_cpu_power3
    },
	{	/* I-star */
		0xffff0000, 0x00360000, "I-star",
		CPU_FTR_COMMON |
		CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
		COMMON_PPC | PPC_FEATURE_64,
		128, 128,
		__setup_cpu_power3
	},
	{	/* S-star */
		0xffff0000, 0x00370000, "S-star",
		CPU_FTR_COMMON |
		CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
		COMMON_PPC | PPC_FEATURE_64,
		128, 128,
		__setup_cpu_power3
	},
#endif /* CONFIG_PPC64BRIDGE */
#ifdef CONFIG_POWER4
    {	/* Power4 */
    	0xffff0000, 0x00350000, "Power4",
	CPU_FTR_COMMON |
    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
    	COMMON_PPC | PPC_FEATURE_64,
	128, 128,
	__setup_cpu_power4
    },
    {	/* PPC970 */
	0xffff0000, 0x00390000, "PPC970",
	CPU_FTR_COMMON |
	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
	CPU_FTR_ALTIVEC_COMP | CPU_FTR_MAYBE_CAN_NAP,
	COMMON_PPC | PPC_FEATURE_64 | PPC_FEATURE_ALTIVEC_COMP,
	128, 128,
	__setup_cpu_ppc970
    },
    {	/* PPC970FX */
	0xffff0000, 0x003c0000, "PPC970FX",
	CPU_FTR_COMMON |
	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
	CPU_FTR_ALTIVEC_COMP | CPU_FTR_MAYBE_CAN_NAP,
	COMMON_PPC | PPC_FEATURE_64 | PPC_FEATURE_ALTIVEC_COMP,
	128, 128,
	__setup_cpu_ppc970
    },
#endif /* CONFIG_POWER4 */
#ifdef CONFIG_8xx
    {	/* 8xx */
    	0xffff0000, 0x00500000, "8xx",
		/* CPU_FTR_MAYBE_CAN_DOZE is possible,
		 * if the 8xx code is there.... */
    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
    	PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 	16, 16,
	__setup_cpu_8xx	/* Empty */
    },
#endif /* CONFIG_8xx */
#ifdef CONFIG_40x
    {	/* 403GC */
    	0xffffff00, 0x00200200, "403GC",
    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
    	PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
	16, 16,
	0, /*__setup_cpu_403 */
    },
    {	/* 403GCX */
    	0xffffff00, 0x00201400, "403GCX",
    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
    	PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
	16, 16,
	0, /*__setup_cpu_403 */
    },
    {	/* 403G ?? */
    	0xffff0000, 0x00200000, "403G ??",
    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
    	PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
	16, 16,
	0, /*__setup_cpu_403 */
    },
    {	/* 405GP */
    	0xffff0000, 0x40110000, "405GP",
    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
    	PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
	32, 32,
	0, /*__setup_cpu_405 */
    },
    {	/* STB 03xxx */
    	0xffff0000, 0x40130000, "STB03xxx",
    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
    	PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
	32, 32,
	0, /*__setup_cpu_405 */
    },
    {	/* STB 04xxx */
    	0xffff0000, 0x41810000, "STB04xxx",
    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
    	PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
	32, 32,
	0, /*__setup_cpu_405 */
    },
    {	/* NP405L */
    	0xffff0000, 0x41610000, "NP405L",
    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
    	PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
	32, 32,
	0, /*__setup_cpu_405 */
    },
    {	/* NP4GS3 */
    	0xffff0000, 0x40B10000, "NP4GS3",
    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
    	PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
	32, 32,
	0, /*__setup_cpu_405 */
    },
    {   /* NP405H */
        0xffff0000, 0x41410000, "NP405H",
        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
        PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
        32, 32,
        0, /*__setup_cpu_405 */
     },
     {	/* 405GPr */
    	0xffff0000, 0x50910000, "405GPr",
    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
    	PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
	32, 32,
	0, /*__setup_cpu_405 */
    },
    {   /* STBx25xx */
        0xffff0000, 0x51510000, "STBx25xx",
        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
        PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
        32, 32,
        0, /*__setup_cpu_405 */
     },
     {	/* 405LP */
    	0xffff0000, 0x41F10000, "405LP",
    	CPU_FTR_SPLIT_ID_CACHE |  CPU_FTR_USE_TB,
    	PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
	32, 32,
	0, /*__setup_cpu_405 */
     },
     {	/* Xilinx Virtex-II Pro  */
	0xffff0000, 0x20010000, "Virtex-II Pro",
	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
	PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
	32, 32,
	0, /*__setup_cpu_405 */
     },

#endif /* CONFIG_40x */
#ifdef CONFIG_44x
    { /* 440GP Rev. B */
        0xf0000fff, 0x40000440, "440GP Rev. B",
        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
        PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
        32, 32,
        0, /*__setup_cpu_440 */
    },
    { /* 440GP Rev. C */
        0xf0000fff, 0x40000481, "440GP Rev. C",
        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
        PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
        32, 32,
        0, /*__setup_cpu_440 */
    },
    { /* 440GX Rev. A */
        0xf0000fff, 0x50000850, "440GX Rev. A",
        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
        PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
        32, 32,
        0, /*__setup_cpu_440 */
    },
    { /* 440GX Rev. B */
        0xf0000fff, 0x50000851, "440GX Rev. B",
        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
        PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
        32, 32,
        0, /*__setup_cpu_440 */
    },
    { /* 440GX Rev. C */
        0xf0000fff, 0x50000892, "440GX Rev. C",
        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
        PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
        32, 32,
        0, /*__setup_cpu_440 */
    },
#endif /* CONFIG_44x */
#ifdef CONFIG_E500
    { /* e500 */
        0xffff0000, 0x80200000, "e500",
	/* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
        PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
        32, 32,
        0, /*__setup_cpu_e500 */
    },
#endif
#if !CLASSIC_PPC
    {	/* default match */
    	0x00000000, 0x00000000, "(generic PPC)",
	CPU_FTR_COMMON,
    	PPC_FEATURE_32,
	32, 32,
	0,
    }
#endif /* !CLASSIC_PPC */
};