gt64260_common.c

来自「Linux Kernel 2.6.9 for OMAP1710」· C语言 代码 · 共 1,665 行 · 第 1/3 页

		rc = gt64260_pci_slave_set_window(
				hose,
				pci_base_addr,
				other_bus_base_addr,
				size,
				pci_p2p_mem_windows[pci_bus][window][0],
				pci_p2p_mem_windows[pci_bus][window][1],
				pci_p2p_mem_windows[pci_bus][window][2],
				pci_p2p_mem_windows[pci_bus][window][3]);
	}

	return rc;
} /* gt64260_pci_slave_p2p_mem_set_window() */

int
gt64260_pci_slave_p2p_io_set_window(struct pci_controller *hose,
				    u32 pci_base_addr,
				    u32 other_bus_base_addr,
				    u32 size)
{
	int	rc;

	rc = gt64260_pci_slave_set_window(hose,
					  pci_base_addr,
					  other_bus_base_addr,
					  size,
					  2,
					  0x18,
					  GT64260_PCI_1_SLAVE_P2P_IO_SIZE,
					  GT64260_PCI_1_SLAVE_P2P_IO_REMAP);

	return rc;
} /* gt64260_pci_slave_p2p_io_set_window() */

int
gt64260_pci_slave_dac_scs_set_window(struct pci_controller *hose,
				     u32 window,
				     u32 pci_base_addr_hi,
				     u32 pci_base_addr_lo,
				     u32 cpu_base_addr,
				     u32 size)
{
	static u32
	pci_dac_scs_windows[GT64260_PCI_BUSES][GT64260_PCI_DAC_SCS_WINDOWS][5]={
		{ /* PCI 0 */
			{ 4, 0x10, 0x14,
			  GT64260_PCI_0_SLAVE_DAC_SCS_0_SIZE,
			  GT64260_PCI_0_SLAVE_DAC_SCS_0_REMAP },
			{ 4, 0x18, 0x1c,
			  GT64260_PCI_0_SLAVE_DAC_SCS_1_SIZE,
			  GT64260_PCI_0_SLAVE_DAC_SCS_1_REMAP },
			{ 5, 0x10, 0x14,
			  GT64260_PCI_0_SLAVE_DAC_SCS_2_SIZE,
			  GT64260_PCI_0_SLAVE_DAC_SCS_2_REMAP },
			{ 5, 0x18, 0x1c,
			  GT64260_PCI_0_SLAVE_DAC_SCS_3_SIZE,
			  GT64260_PCI_0_SLAVE_DAC_SCS_3_REMAP },
		},
		{ /* PCI 1 */
			{ 4, 0x10, 0x14,
			  GT64260_PCI_1_SLAVE_DAC_SCS_0_SIZE,
			  GT64260_PCI_1_SLAVE_DAC_SCS_0_REMAP },
			{ 4, 0x18, 0x1c,
			  GT64260_PCI_1_SLAVE_DAC_SCS_1_SIZE,
			  GT64260_PCI_1_SLAVE_DAC_SCS_1_REMAP },
			{ 5, 0x10, 0x14,
			  GT64260_PCI_1_SLAVE_DAC_SCS_2_SIZE,
			  GT64260_PCI_1_SLAVE_DAC_SCS_2_REMAP },
			{ 5, 0x18, 0x1c,
			  GT64260_PCI_1_SLAVE_DAC_SCS_3_SIZE,
			  GT64260_PCI_1_SLAVE_DAC_SCS_3_REMAP },
		}
	}; /* pci_dac_scs_windows[][][] */
	int	pci_bus;
	int	rc = -1;

	if (window < GT64260_PCI_DAC_SCS_WINDOWS) {
		pci_bus = (hose->first_busno == 0) ? 0 : 1;

		rc = gt64260_pci_slave_set_window(
				hose,
				pci_base_addr_lo,
				cpu_base_addr,
				size,
				pci_dac_scs_windows[pci_bus][window][0],
				pci_dac_scs_windows[pci_bus][window][1],
				pci_dac_scs_windows[pci_bus][window][3],
				pci_dac_scs_windows[pci_bus][window][4]);

		early_write_config_dword(
			hose,
			hose->first_busno,
			PCI_DEVFN(0, pci_dac_scs_windows[pci_bus][window][0]),
			pci_dac_scs_windows[pci_bus][window][2],
			pci_base_addr_hi);
	}

	return rc;
} /* gt64260_pci_slave_dac_scs_set_window() */

int
gt64260_pci_slave_dac_cs_set_window(struct pci_controller *hose,
				    u32 window,
				    u32 pci_base_addr_hi,
				    u32 pci_base_addr_lo,
				    u32 cpu_base_addr,
				    u32 size)
{
	static u32
	pci_dac_cs_windows[GT64260_PCI_BUSES][GT64260_PCI_DAC_CS_WINDOWS][5] = {
		{ /* PCI 0 */
			{ 6, 0x10, 0x14,
			  GT64260_PCI_0_SLAVE_DAC_CS_0_SIZE,
			  GT64260_PCI_0_SLAVE_DAC_CS_0_REMAP },
			{ 6, 0x18, 0x1c,
			  GT64260_PCI_0_SLAVE_DAC_CS_1_SIZE,
			  GT64260_PCI_0_SLAVE_DAC_CS_1_REMAP },
			{ 6, 0x20, 0x24,
			  GT64260_PCI_0_SLAVE_DAC_CS_2_SIZE,
			  GT64260_PCI_0_SLAVE_DAC_CS_2_REMAP },
			{ 7, 0x10, 0x14,
			  GT64260_PCI_0_SLAVE_DAC_CS_3_SIZE,
			  GT64260_PCI_0_SLAVE_DAC_CS_3_REMAP },
		},
		{ /* PCI 1 */
			{ 6, 0x10, 0x14,
			  GT64260_PCI_1_SLAVE_DAC_CS_0_SIZE,
			  GT64260_PCI_1_SLAVE_DAC_CS_0_REMAP },
			{ 6, 0x18, 0x1c,
			  GT64260_PCI_1_SLAVE_DAC_CS_1_SIZE,
			  GT64260_PCI_1_SLAVE_DAC_CS_1_REMAP },
			{ 6, 0x20, 0x24,
			  GT64260_PCI_1_SLAVE_DAC_CS_2_SIZE,
			  GT64260_PCI_1_SLAVE_DAC_CS_2_REMAP },
			{ 7, 0x10, 0x14,
			  GT64260_PCI_1_SLAVE_DAC_CS_3_SIZE,
			  GT64260_PCI_1_SLAVE_DAC_CS_3_REMAP },
		}
	}; /* pci_dac_cs_windows[][][] */
	int	pci_bus;
	int	rc = -1;

	if (window < GT64260_PCI_CS_WINDOWS) {
		pci_bus = (hose->first_busno == 0) ? 0 : 1;

		rc = gt64260_pci_slave_set_window(
				hose,
				pci_base_addr_lo,
				cpu_base_addr,
				size,
				pci_dac_cs_windows[pci_bus][window][0],
				pci_dac_cs_windows[pci_bus][window][1],
				pci_dac_cs_windows[pci_bus][window][3],
				pci_dac_cs_windows[pci_bus][window][4]);

		early_write_config_dword(
			hose,
			hose->first_busno,
			PCI_DEVFN(0, pci_dac_cs_windows[pci_bus][window][0]),
			pci_dac_cs_windows[pci_bus][window][2],
			pci_base_addr_hi);
	}

	return rc;
} /* gt64260_pci_slave_dac_cs_set_window() */

int
gt64260_pci_slave_dac_boot_set_window(struct pci_controller *hose,
				      u32 pci_base_addr_hi,
				      u32 pci_base_addr_lo,
				      u32 cpu_base_addr,
				      u32 size)
{
	int	rc;

	rc = gt64260_pci_slave_set_window(hose,
					  pci_base_addr_lo,
					  cpu_base_addr,
					  size,
					  7,
					  0x18,
					  GT64260_PCI_1_SLAVE_BOOT_SIZE,
					  GT64260_PCI_1_SLAVE_BOOT_REMAP);

	early_write_config_dword(hose,
				 hose->first_busno,
				 PCI_DEVFN(0, 7),
				 0x1c,
				 pci_base_addr_hi);

	return rc;
} /* gt64260_pci_slave_dac_boot_set_window() */

int
gt64260_pci_slave_dac_p2p_mem_set_window(struct pci_controller *hose,
				         u32 window,
				         u32 pci_base_addr_hi,
				         u32 pci_base_addr_lo,
				         u32 other_bus_base_addr,
				         u32 size)
{
	static u32
	pci_dac_p2p_mem_windows[GT64260_PCI_BUSES][GT64260_PCI_DAC_P2P_MEM_WINDOWS][5] = {
		{ /* PCI 0 */
			{ 4, 0x20, 0x24,
			  GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_SIZE,
			  GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_REMAP_LO },
			{ 5, 0x20, 0x24,
			  GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_SIZE,
			  GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_REMAP_LO },
		},
		{ /* PCI 1 */
			{ 4, 0xa0, 0xa4,
			  GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_SIZE,
			  GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_REMAP_LO },
			{ 5, 0xa0, 0xa4,
			  GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_SIZE,
			  GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_REMAP_LO },
		}
	}; /* pci_dac_p2p_windows[][][] */
	int	pci_bus;
	int	rc = -1;

	if (window < GT64260_PCI_P2P_MEM_WINDOWS) {
		pci_bus = (hose->first_busno == 0) ? 0 : 1;

		rc = gt64260_pci_slave_set_window(
				hose,
				pci_base_addr_lo,
				other_bus_base_addr,
				size,
				pci_dac_p2p_mem_windows[pci_bus][window][0],
				pci_dac_p2p_mem_windows[pci_bus][window][1],
				pci_dac_p2p_mem_windows[pci_bus][window][3],
				pci_dac_p2p_mem_windows[pci_bus][window][4]);

		early_write_config_dword(
		    hose,
		    hose->first_busno,
		    PCI_DEVFN(0, pci_dac_p2p_mem_windows[pci_bus][window][0]),
		    pci_dac_p2p_mem_windows[pci_bus][window][2],
		    pci_base_addr_hi);
	}

	return rc;
} /* gt64260_pci_slave_dac_p2p_mem_set_window() */


/*
 *****************************************************************************
 *
 *	PCI Control Configuration Routines
 *
 *****************************************************************************
 */


int
gt64260_pci_acc_cntl_set_window(u32 pci_bus,
			        u32 window,
			        u32 base_addr_hi,
			        u32 base_addr_lo,
			        u32 size,
			        u32 features)
{
	static u32
	pci_acc_cntl_windows[GT64260_PCI_BUSES][GT64260_PCI_ACC_CNTL_WINDOWS][3] = {
		{ /* PCI 0 */
			{ GT64260_PCI_0_ACC_CNTL_0_BASE_HI,
			  GT64260_PCI_0_ACC_CNTL_0_BASE_LO,
			  GT64260_PCI_0_ACC_CNTL_0_TOP },

			{ GT64260_PCI_0_ACC_CNTL_1_BASE_HI,
			  GT64260_PCI_0_ACC_CNTL_1_BASE_LO,
			  GT64260_PCI_0_ACC_CNTL_1_TOP },

			{ GT64260_PCI_0_ACC_CNTL_2_BASE_HI,
			  GT64260_PCI_0_ACC_CNTL_2_BASE_LO,
			  GT64260_PCI_0_ACC_CNTL_2_TOP },

			{ GT64260_PCI_0_ACC_CNTL_3_BASE_HI,
			  GT64260_PCI_0_ACC_CNTL_3_BASE_LO,
			  GT64260_PCI_0_ACC_CNTL_3_TOP },

			{ GT64260_PCI_0_ACC_CNTL_4_BASE_HI,
			  GT64260_PCI_0_ACC_CNTL_4_BASE_LO,
			  GT64260_PCI_0_ACC_CNTL_4_TOP },

			{ GT64260_PCI_0_ACC_CNTL_5_BASE_HI,
			  GT64260_PCI_0_ACC_CNTL_5_BASE_LO,
			  GT64260_PCI_0_ACC_CNTL_5_TOP },

			{ GT64260_PCI_0_ACC_CNTL_6_BASE_HI,
			  GT64260_PCI_0_ACC_CNTL_6_BASE_LO,
			  GT64260_PCI_0_ACC_CNTL_6_TOP },

			{ GT64260_PCI_0_ACC_CNTL_7_BASE_HI,
			  GT64260_PCI_0_ACC_CNTL_7_BASE_LO,
			  GT64260_PCI_0_ACC_CNTL_7_TOP },
		},
		{ /* PCI 1 */
			{ GT64260_PCI_1_ACC_CNTL_0_BASE_HI,
			  GT64260_PCI_1_ACC_CNTL_0_BASE_LO,
			  GT64260_PCI_1_ACC_CNTL_0_TOP },

			{ GT64260_PCI_1_ACC_CNTL_1_BASE_HI,
			  GT64260_PCI_1_ACC_CNTL_1_BASE_LO,
			  GT64260_PCI_1_ACC_CNTL_1_TOP },

			{ GT64260_PCI_1_ACC_CNTL_2_BASE_HI,
			  GT64260_PCI_1_ACC_CNTL_2_BASE_LO,
			  GT64260_PCI_1_ACC_CNTL_2_TOP },

			{ GT64260_PCI_1_ACC_CNTL_3_BASE_HI,
			  GT64260_PCI_1_ACC_CNTL_3_BASE_LO,
			  GT64260_PCI_1_ACC_CNTL_3_TOP },

			{ GT64260_PCI_1_ACC_CNTL_4_BASE_HI,
			  GT64260_PCI_1_ACC_CNTL_4_BASE_LO,
			  GT64260_PCI_1_ACC_CNTL_4_TOP },

			{ GT64260_PCI_1_ACC_CNTL_5_BASE_HI,
			  GT64260_PCI_1_ACC_CNTL_5_BASE_LO,
			  GT64260_PCI_1_ACC_CNTL_5_TOP },

			{ GT64260_PCI_1_ACC_CNTL_6_BASE_HI,
			  GT64260_PCI_1_ACC_CNTL_6_BASE_LO,
			  GT64260_PCI_1_ACC_CNTL_6_TOP },

			{ GT64260_PCI_1_ACC_CNTL_7_BASE_HI,
			  GT64260_PCI_1_ACC_CNTL_7_BASE_LO,
			  GT64260_PCI_1_ACC_CNTL_7_TOP },
		}
	}; /* pci_acc_cntl_windows[][][] */
	int	rc = -1;

	if ((pci_bus < GT64260_PCI_BUSES) &&
	    (window < GT64260_PCI_ACC_CNTL_WINDOWS)) {

		rc = gt64260_set_64bit_window(
			      base_addr_hi,
			      base_addr_lo,
			      size,
			      features,
			      pci_acc_cntl_windows[pci_bus][window][0],
			      pci_acc_cntl_windows[pci_bus][window][1],
			      pci_acc_cntl_windows[pci_bus][window][2]);
	}

	return rc;
} /* gt64260_pci_acc_cntl_set_window() */

int
gt64260_pci_snoop_set_window(u32 pci_bus,
			     u32 window,
			     u32 base_addr_hi,
			     u32 base_addr_lo,
			     u32 size,
			     u32 snoop_type)
{
	static u32
	pci_snoop_windows[GT64260_PCI_BUSES][GT64260_PCI_SNOOP_WINDOWS][3] = {
		{ /* PCI 0 */
			{ GT64260_PCI_0_SNOOP_0_BASE_HI,
			  GT64260_PCI_0_SNOOP_0_BASE_LO,
			  GT64260_PCI_0_SNOOP_0_TOP },

			{ GT64260_PCI_0_SNOOP_1_BASE_HI,
			  GT64260_PCI_0_SNOOP_1_BASE_LO,
			  GT64260_PCI_0_SNOOP_1_TOP },

			{ GT64260_PCI_0_SNOOP_2_BASE_HI,
			  GT64260_PCI_0_SNOOP_2_BASE_LO,
			  GT64260_PCI_0_SNOOP_2_TOP },

			{ GT64260_PCI_0_SNOOP_3_BASE_HI,
			  GT64260_PCI_0_SNOOP_3_BASE_LO,
			  GT64260_PCI_0_SNOOP_3_TOP },
		},
		{ /* PCI 1 */
			{ GT64260_PCI_1_SNOOP_0_BASE_HI,
			  GT64260_PCI_1_SNOOP_0_BASE_LO,
			  GT64260_PCI_1_SNOOP_0_TOP },

			{ GT64260_PCI_1_SNOOP_1_BASE_HI,
			  GT64260_PCI_1_SNOOP_1_BASE_LO,
			  GT64260_PCI_1_SNOOP_1_TOP },

			{ GT64260_PCI_1_SNOOP_2_BASE_HI,
			  GT64260_PCI_1_SNOOP_2_BASE_LO,
			  GT64260_PCI_1_SNOOP_2_TOP },

			{ GT64260_PCI_1_SNOOP_3_BASE_HI,
			  GT64260_PCI_1_SNOOP_3_BASE_LO,
			  GT64260_PCI_1_SNOOP_3_TOP },
		},
	}; /* pci_snoop_windows[][][] */
	int	rc = -1;

	if ((pci_bus < GT64260_PCI_BUSES) &&
	    (window < GT64260_PCI_SNOOP_WINDOWS)) {

		rc = gt64260_set_64bit_window(
			      base_addr_hi,
			      base_addr_lo,
			      size,
			      snoop_type,
			      pci_snoop_windows[pci_bus][window][0],
			      pci_snoop_windows[pci_bus][window][1],
			      pci_snoop_windows[pci_bus][window][2]);
	}

	return rc;
} /* gt64260_pci_snoop_set_window() */

/*
 *****************************************************************************
 *
 *	64260's Register Base Address Routines
 *
 *****************************************************************************
 */

/*
 * gt64260_remap_bridge_regs()
 *
 * Move the bridge's register to the specified base address.
 * Assume that there are no other windows overlapping this area and that
 * all but the highest 3 nibbles are 0.
 */
int
gt64260_set_base(u32 new_base)
{
	u32	val;
	int	limit = 100000;
	int	rc = 0;

	val = gt_read(GT64260_INTERNAL_SPACE_DECODE);
	val = (new_base >> 20) | (val & 0xffff0000);
	gt_write(GT64260_INTERNAL_SPACE_DECODE, val);

	iounmap((void *)gt64260_base);
	gt64260_base = (u32)ioremap((new_base & 0xfff00000),
				    GT64260_INTERNAL_SPACE_SIZE);

	do { /* Wait for bridge to move its regs */
		val = gt_read(GT64260_INTERNAL_SPACE_DECODE);
	} while ((val != 0xffffffff) && (limit-- > 0));

	if (limit <= 0) {
		rc = -1;
	}

	return rc;
} /* gt64260_remap_bridge_regs() */

/*
 * gt64260_get_base()
 *
 * Return the current virtual base address of the 64260's registers.
 */
int
gt64260_get_base(u32 *base)
{
	*base = gt64260_base;
	return 0;
} /* gt64260_remap_bridge_regs() */

/*
 *****************************************************************************
 *
 *	Exclude PCI config space access to bridge itself
 *
 *****************************************************************************
 */

/*
 * gt64260_exclude_pci_device()
 *
 * This routine causes the PCI subsystem to skip the PCI device in slot 0
 * (which is the 64260 itself) unless explicitly allowed.
 */
int
gt64260_pci_exclude_device(u8 bus, u8 devfn)
{
	struct pci_controller	*hose;

	hose = pci_bus_to_hose(bus);

	/* Skip slot 0 and 1 on both hoses */
	if ((gt64260_pci_exclude_bridge == TRUE) &&
	    (PCI_SLOT(devfn) == 0) &&
	    (hose->first_busno == bus)) {

		return PCIBIOS_DEVICE_NOT_FOUND;
	}
	else {
		return PCIBIOS_SUCCESSFUL;
	}
} /* gt64260_pci_exclude_device() */

#if defined(CONFIG_SERIAL_TEXT_DEBUG)

/*
 * gt64260_putc()
 *
 * Dump a character out the MPSC port for gt64260_mpsc_progress
 * this assumes the baud rate has already been set up and the
 * MPSC initialized by the bootloader or firmware.
 */

static inline void
gt_putc(char c){
	mb();
	gt_write(GT64260_MPSC_0_CHR_1, c);
	mb();
	gt_write(GT64260_MPSC_0_CHR_2, 0x200);
	mb();

	udelay(10000);
}

void
puthex(unsigned long val){

        int i;

        for (i = 7;  i >= 0;  i--) {
		gt_putc("0123456789ABCDEF"[(val>>28) & 0x0f]);
		val <<= 4;
	}
	gt_putc('\r');
	gt_putc('\n');

}


void
gt64260_mpsc_progress(char *s, unsigned short hex){
	/* spit stuff out the 64260 mpsc */

	volatile char	c;
	while ((c = *s++) != 0){
		gt_putc(c);
		if ( c == '\n' ) gt_putc('\r');
	}
	gt_putc('\n');
	gt_putc('\r');

	return;
}

#endif /* CONFIG_DEBUG_TEXT */