gt64260_common.c

来自「Linux Kernel 2.6.9 for OMAP1710」· C语言 代码 · 共 1,665 行 · 第 1/3 页

	cpu_scs_windows[GT64260_CPU_SCS_DECODE_WINDOWS][2] = {
		{ GT64260_CPU_SCS_DECODE_0_BOT, GT64260_CPU_SCS_DECODE_0_TOP },
		{ GT64260_CPU_SCS_DECODE_1_BOT, GT64260_CPU_SCS_DECODE_1_TOP },
		{ GT64260_CPU_SCS_DECODE_2_BOT, GT64260_CPU_SCS_DECODE_2_TOP },
		{ GT64260_CPU_SCS_DECODE_3_BOT, GT64260_CPU_SCS_DECODE_3_TOP },
	}; /* cpu_scs_windows[][] */
	int	rc = -1;

	if (window < GT64260_CPU_SCS_DECODE_WINDOWS) {
		rc = gt64260_set_32bit_window(base_addr,
					      size,
					      0,
					      cpu_scs_windows[window][0],
					      cpu_scs_windows[window][1]);
	}

	return rc;
} /* gt64260_cpu_scs_set_window() */

int
gt64260_cpu_cs_set_window(u32 window,
			  u32 base_addr,
			  u32 size)
{
	static u32
	cpu_cs_windows[GT64260_CPU_CS_DECODE_WINDOWS][2] = {
		{ GT64260_CPU_CS_DECODE_0_BOT, GT64260_CPU_CS_DECODE_0_TOP },
		{ GT64260_CPU_CS_DECODE_1_BOT, GT64260_CPU_CS_DECODE_1_TOP },
		{ GT64260_CPU_CS_DECODE_2_BOT, GT64260_CPU_CS_DECODE_2_TOP },
		{ GT64260_CPU_CS_DECODE_3_BOT, GT64260_CPU_CS_DECODE_3_TOP },
	}; /* cpu_cs_windows[][] */
	int	rc = -1;

	if (window < GT64260_CPU_CS_DECODE_WINDOWS) {
		rc = gt64260_set_32bit_window(base_addr,
					      size,
					      0,
					      cpu_cs_windows[window][0],
					      cpu_cs_windows[window][1]);
	}

	return rc;
} /* gt64260_cpu_cs_set_window() */

int
gt64260_cpu_boot_set_window(u32 base_addr,
			    u32 size)
{
	int	rc;

	rc = gt64260_set_32bit_window(base_addr,
				      size,
				      0,
				      GT64260_CPU_BOOT_CS_DECODE_0_BOT,
				      GT64260_CPU_BOOT_CS_DECODE_0_TOP);

	return rc;
} /* gt64260_cpu_boot_set_window() */

/*
 * gt64260_cpu_set_pci_io_window()
 *
 * Set up a CPU window into PCI I/O or MEM space.
 * Always do Read/Modify/Write to window regs.
 */
static int
gt64260_cpu_pci_set_window(u32 cpu_base_addr,
			   u32 pci_base_addr,
			   u32 size,
			   u32 other_bits,
			   u32 bot_reg,
			   u32 top_reg,
			   u32 remap_reg)
{
	u32	val;
	int	rc;

	if ((rc = gt64260_set_32bit_window(cpu_base_addr,
					   size,
					   other_bits,
					   bot_reg,
					   top_reg)) == 0) {

		/* Set up CPU->PCI remapping (on lower 32 bits) */
		gt_write(remap_reg, pci_base_addr >> 20);
		val = gt_read(bot_reg); /* Flush FIFO */
	}

	return rc;
} /* gt64260_cpu_pci_set_window() */


/*
 * gt64260_cpu_set_pci_io_window()
 *
 * Set up a CPU window into PCI I/O space.
 * Always do Read/Modify/Write to window regs.
 */
int
gt64260_cpu_set_pci_io_window(u32 pci_bus,
			      u32 cpu_base_addr,
			      u32 pci_base_addr,
			      u32 size,
			      u32 swap)
{
	/* 2 PCI buses with 1 I/O window each (from CPU point of view) */
	static u32
	cpu_pci_io_windows[GT64260_PCI_BUSES][3] = {
		{ GT64260_CPU_PCI_0_IO_DECODE_BOT,
		  GT64260_CPU_PCI_0_IO_DECODE_TOP,
		  GT64260_CPU_PCI_0_IO_REMAP },

		{ GT64260_CPU_PCI_1_IO_DECODE_BOT,
		  GT64260_CPU_PCI_1_IO_DECODE_TOP,
		  GT64260_CPU_PCI_1_IO_REMAP },
	}; /* cpu_pci_io_windows[][] */
	int	rc = -1;

	if (pci_bus < GT64260_PCI_BUSES) {
		rc =  gt64260_cpu_pci_set_window(cpu_base_addr,
					  pci_base_addr,
					  size,
					  swap,
					  cpu_pci_io_windows[pci_bus][0],
					  cpu_pci_io_windows[pci_bus][1],
					  cpu_pci_io_windows[pci_bus][2]);
	}

	return rc;
} /* gt64260_cpu_set_pci_io_window() */

/*
 * gt64260_cpu_set_pci_mem_window()
 *
 * Set up a CPU window into PCI MEM space (4 PCI MEM windows per PCI bus).
 * Always do Read/Modify/Write to window regs.
 */
int
gt64260_cpu_set_pci_mem_window(u32 pci_bus,
			       u32 window,
			       u32 cpu_base_addr,
			       u32 pci_base_addr_hi,
			       u32 pci_base_addr_lo,
			       u32 size,
			       u32 swap_64bit)
{
	/* 2 PCI buses with 4 memory windows each (from CPU point of view) */
	static u32
	cpu_pci_mem_windows[GT64260_PCI_BUSES][GT64260_PCI_MEM_WINDOWS_PER_BUS][4] = {
		{ /* PCI 0 */
			{ GT64260_CPU_PCI_0_MEM_0_DECODE_BOT,
			  GT64260_CPU_PCI_0_MEM_0_DECODE_TOP,
			  GT64260_CPU_PCI_0_MEM_0_REMAP_HI,
			  GT64260_CPU_PCI_0_MEM_0_REMAP_LO },

			{ GT64260_CPU_PCI_0_MEM_1_DECODE_BOT,
			  GT64260_CPU_PCI_0_MEM_1_DECODE_TOP,
			  GT64260_CPU_PCI_0_MEM_1_REMAP_HI,
			  GT64260_CPU_PCI_0_MEM_1_REMAP_LO },

			{ GT64260_CPU_PCI_0_MEM_2_DECODE_BOT,
			  GT64260_CPU_PCI_0_MEM_2_DECODE_TOP,
			  GT64260_CPU_PCI_0_MEM_2_REMAP_HI,
			  GT64260_CPU_PCI_0_MEM_2_REMAP_LO },

			{ GT64260_CPU_PCI_0_MEM_3_DECODE_BOT,
			  GT64260_CPU_PCI_0_MEM_3_DECODE_TOP,
			  GT64260_CPU_PCI_0_MEM_3_REMAP_HI,
			  GT64260_CPU_PCI_0_MEM_3_REMAP_LO }
		},

		{ /* PCI 1 */
			{ GT64260_CPU_PCI_1_MEM_0_DECODE_BOT,
			  GT64260_CPU_PCI_1_MEM_0_DECODE_TOP,
			  GT64260_CPU_PCI_1_MEM_0_REMAP_HI,
			  GT64260_CPU_PCI_1_MEM_0_REMAP_LO },

			{ GT64260_CPU_PCI_1_MEM_1_DECODE_BOT,
			  GT64260_CPU_PCI_1_MEM_1_DECODE_TOP,
			  GT64260_CPU_PCI_1_MEM_1_REMAP_HI,
			  GT64260_CPU_PCI_1_MEM_1_REMAP_LO },

			{ GT64260_CPU_PCI_1_MEM_2_DECODE_BOT,
			  GT64260_CPU_PCI_1_MEM_2_DECODE_TOP,
			  GT64260_CPU_PCI_1_MEM_2_REMAP_HI,
			  GT64260_CPU_PCI_1_MEM_2_REMAP_LO },

			{ GT64260_CPU_PCI_1_MEM_3_DECODE_BOT,
			  GT64260_CPU_PCI_1_MEM_3_DECODE_TOP,
			  GT64260_CPU_PCI_1_MEM_3_REMAP_HI,
			  GT64260_CPU_PCI_1_MEM_3_REMAP_LO },
		}
	}; /* cpu_pci_mem_windows[][][] */
	u32		remap_reg, remap;
	int		rc = -1;

	if ((pci_bus < GT64260_PCI_BUSES) &&
	    (window < GT64260_PCI_MEM_WINDOWS_PER_BUS)) {

		if (gt64260_cpu_pci_set_window(
			cpu_base_addr,
			pci_base_addr_lo,
			size,
			swap_64bit,
			cpu_pci_mem_windows[pci_bus][window][0],
			cpu_pci_mem_windows[pci_bus][window][1],
			cpu_pci_mem_windows[pci_bus][window][3]) == 0) {

			remap_reg = cpu_pci_mem_windows[pci_bus][window][2];
			gt_write(remap_reg, pci_base_addr_hi);

			remap = gt_read(remap_reg); /* Flush FIFO */

			rc = 0;
		}
	}

	return rc;
} /* gt64260_cpu_set_pci_mem_window() */

int
gt64260_cpu_prot_set_window(u32 window,
			    u32 base_addr,
			    u32 size,
			    u32 access_bits)
{
	static u32
	cpu_prot_windows[GT64260_CPU_PROT_WINDOWS][2] = {
		{ GT64260_CPU_PROT_BASE_0, GT64260_CPU_PROT_TOP_0 },
		{ GT64260_CPU_PROT_BASE_1, GT64260_CPU_PROT_TOP_1 },
		{ GT64260_CPU_PROT_BASE_2, GT64260_CPU_PROT_TOP_2 },
		{ GT64260_CPU_PROT_BASE_3, GT64260_CPU_PROT_TOP_3 },
		{ GT64260_CPU_PROT_BASE_4, GT64260_CPU_PROT_TOP_4 },
		{ GT64260_CPU_PROT_BASE_5, GT64260_CPU_PROT_TOP_5 },
		{ GT64260_CPU_PROT_BASE_6, GT64260_CPU_PROT_TOP_6 },
		{ GT64260_CPU_PROT_BASE_7, GT64260_CPU_PROT_TOP_7 },
	}; /* cpu_prot_windows[][] */
	int	rc = -1;

	if (window < GT64260_CPU_PROT_WINDOWS) {
		rc = gt64260_set_32bit_window(base_addr,
					      size,
					      access_bits,
					      cpu_prot_windows[window][0],
					      cpu_prot_windows[window][1]);
	}

	return rc;
} /* gt64260_cpu_prot_set_window() */

int
gt64260_cpu_snoop_set_window(u32 window,
			     u32 base_addr,
			     u32 size,
			     u32  snoop_type)
{
	static u32
	cpu_snoop_windows[GT64260_CPU_SNOOP_WINDOWS][2] = {
		{ GT64260_CPU_SNOOP_BASE_0, GT64260_CPU_SNOOP_TOP_0 },
		{ GT64260_CPU_SNOOP_BASE_1, GT64260_CPU_SNOOP_TOP_1 },
		{ GT64260_CPU_SNOOP_BASE_2, GT64260_CPU_SNOOP_TOP_2 },
		{ GT64260_CPU_SNOOP_BASE_3, GT64260_CPU_SNOOP_TOP_3 },
	}; /* cpu_snoop_windows[][] */
	int	rc = -1;

	if ((window < GT64260_CPU_SNOOP_WINDOWS) &&
	    (snoop_type <= GT64260_CPU_SNOOP_WB)) {

		rc = gt64260_set_32bit_window(base_addr,
					      size,
					      snoop_type,
					      cpu_snoop_windows[window][0],
					      cpu_snoop_windows[window][1]);
	}

	return rc;
} /* gt64260_cpu_snoop_set_window() */

void
gt64260_cpu_disable_all_windows(void)
{
	int	pci_bus, window;

	/* Don't disable SCS windows b/c we need to access system memory */

	for (window=0; window<GT64260_CPU_CS_DECODE_WINDOWS; window++) {
		gt64260_cpu_cs_set_window(window, 0, 0);
	}

	gt64260_cpu_boot_set_window(0, 0);

	for (pci_bus=0; pci_bus<GT64260_PCI_BUSES; pci_bus++) {
		gt64260_cpu_set_pci_io_window(pci_bus, 0, 0, 0, 0);

		for (window=0;window<GT64260_PCI_MEM_WINDOWS_PER_BUS;window++) {
			gt64260_cpu_set_pci_mem_window(pci_bus,
						       window,
						       0, 0, 0, 0, 0);
		}
	}

	for (window=0; window<GT64260_CPU_PROT_WINDOWS; window++) {
		gt64260_cpu_prot_set_window(window, 0, 0, 0);
	}

	for (window=0; window<GT64260_CPU_SNOOP_WINDOWS; window++) {
		gt64260_cpu_snoop_set_window(window, 0, 0, 0);
	}

	return;
} /* gt64260_cpu_disable_all_windows() */


/*
 *****************************************************************************
 *
 *	PCI Slave Window Configuration Routines
 *
 *****************************************************************************
 */

int
gt64260_pci_bar_enable(u32 pci_bus,
		       u32 enable_bits)
{
	u32	reg, val;
	int	rc = -1;

	if (pci_bus < GT64260_PCI_BUSES) {
		reg = (pci_bus == 0) ? GT64260_PCI_0_SLAVE_BAR_REG_ENABLES :
				       GT64260_PCI_1_SLAVE_BAR_REG_ENABLES;


		/* Note: '0' enables, '1' disables */
		val = gt_read(reg);
		val |= 0xffffffff;	/* Disable everything by default */
		val &= ~enable_bits;
		gt_write(reg, val);

		gt_read(reg); /* Flush FIFO */

		rc = 0;
	}

	return rc;
} /* gt64260_pci_bar_enable() */

static int
gt64260_pci_slave_set_window(struct pci_controller *hose,
			     u32 pci_base_addr,
			     u32 cpu_base_addr,
			     u32 bar_size,
			     u32 pci_cfg_fcn,
			     u32 pci_cfg_hdr_offset,
			     u32 bar_size_reg,
			     u32 remap_reg)
{
	u32	val;
	int	devfn;
	u8	save_exclude;

	pci_base_addr &= 0xfffff000;
	cpu_base_addr &= 0xfffff000;
	bar_size &= 0xfffff000;
	devfn = PCI_DEVFN(0, pci_cfg_fcn);

	gt_write(bar_size_reg, (bar_size - 1) & 0xfffff000);
	gt_write(remap_reg, cpu_base_addr);
	gt_read(remap_reg); /* Flush FIFO */

	save_exclude = gt64260_pci_exclude_bridge;
	gt64260_pci_exclude_bridge = FALSE;
	early_read_config_dword(hose,
				hose->first_busno,
				devfn,
				pci_cfg_hdr_offset,
				&val);
	val &= 0x0000000f;
	early_write_config_dword(hose,
				 hose->first_busno,
				 devfn,
				 pci_cfg_hdr_offset,
				 pci_base_addr | val);
	gt64260_pci_exclude_bridge = save_exclude;

	return 0;
} /* gt64260_pci_slave_set_window() */

int
gt64260_pci_slave_scs_set_window(struct pci_controller *hose,
				 u32 window,
				 u32 pci_base_addr,
				 u32 cpu_base_addr,
				 u32 size)
{
	static u32
	pci_scs_windows[GT64260_PCI_BUSES][GT64260_PCI_SCS_WINDOWS][4] = {
		{ /* PCI 0 */
			{ 0, 0x10,
			  GT64260_PCI_0_SLAVE_SCS_0_SIZE,
			  GT64260_PCI_0_SLAVE_SCS_0_REMAP },
			{ 0, 0x14,
			  GT64260_PCI_0_SLAVE_SCS_1_SIZE,
			  GT64260_PCI_0_SLAVE_SCS_1_REMAP },
			{ 0, 0x18,
			  GT64260_PCI_0_SLAVE_SCS_2_SIZE,
			  GT64260_PCI_0_SLAVE_SCS_2_REMAP },
			{ 0, 0x1c,
			  GT64260_PCI_0_SLAVE_SCS_3_SIZE,
			  GT64260_PCI_0_SLAVE_SCS_3_REMAP },
		},
		{ /* PCI 1 */
			{ 0, 0x10,
			  GT64260_PCI_1_SLAVE_SCS_0_SIZE,
			  GT64260_PCI_1_SLAVE_SCS_0_REMAP },
			{ 0, 0x14,
			  GT64260_PCI_1_SLAVE_SCS_1_SIZE,
			  GT64260_PCI_1_SLAVE_SCS_1_REMAP },
			{ 0, 0x18,
			  GT64260_PCI_1_SLAVE_SCS_2_SIZE,
			  GT64260_PCI_1_SLAVE_SCS_2_REMAP },
			{ 0, 0x1c,
			  GT64260_PCI_1_SLAVE_SCS_3_SIZE,
			  GT64260_PCI_1_SLAVE_SCS_3_REMAP },
		}
	}; /* pci_scs_windows[][][] */
	int	pci_bus;
	int	rc = -1;

	if (window < GT64260_PCI_SCS_WINDOWS) {
		pci_bus = (hose->first_busno == 0) ? 0 : 1;

		rc = gt64260_pci_slave_set_window(
				hose,
				pci_base_addr,
				cpu_base_addr,
				size,
				pci_scs_windows[pci_bus][window][0],
				pci_scs_windows[pci_bus][window][1],
				pci_scs_windows[pci_bus][window][2],
				pci_scs_windows[pci_bus][window][3]);
	}

	return rc;
} /* gt64260_pci_slave_scs_set_window() */

int
gt64260_pci_slave_cs_set_window(struct pci_controller *hose,
				u32 window,
				u32 pci_base_addr,
				u32 cpu_base_addr,
				u32 size)
{
	static u32
	pci_cs_windows[GT64260_PCI_BUSES][GT64260_PCI_CS_WINDOWS][4] = {
		{ /* PCI 0 */
			{ 1, 0x10,
			  GT64260_PCI_0_SLAVE_CS_0_SIZE,
			  GT64260_PCI_0_SLAVE_CS_0_REMAP },
			{ 1, 0x14,
			  GT64260_PCI_0_SLAVE_CS_1_SIZE,
			  GT64260_PCI_0_SLAVE_CS_1_REMAP },
			{ 1, 0x18,
			  GT64260_PCI_0_SLAVE_CS_2_SIZE,
			  GT64260_PCI_0_SLAVE_CS_2_REMAP },
			{ 1, 0x1c,
			  GT64260_PCI_0_SLAVE_CS_3_SIZE,
			  GT64260_PCI_0_SLAVE_CS_3_REMAP },
		},
		{ /* PCI 1 */
			{ 1, 0x10,
			  GT64260_PCI_1_SLAVE_CS_0_SIZE,
			  GT64260_PCI_1_SLAVE_CS_0_REMAP },
			{ 1, 0x14,
			  GT64260_PCI_1_SLAVE_CS_1_SIZE,
			  GT64260_PCI_1_SLAVE_CS_1_REMAP },
			{ 1, 0x18,
			  GT64260_PCI_1_SLAVE_CS_2_SIZE,
			  GT64260_PCI_1_SLAVE_CS_2_REMAP },
			{ 1, 0x1c,
			  GT64260_PCI_1_SLAVE_CS_3_SIZE,
			  GT64260_PCI_1_SLAVE_CS_3_REMAP },
		}
	}; /* pci_cs_windows[][][] */
	int	pci_bus;
	int	rc = -1;

	if (window < GT64260_PCI_CS_WINDOWS) {
		pci_bus = (hose->first_busno == 0) ? 0 : 1;

		rc = gt64260_pci_slave_set_window(
				hose,
				pci_base_addr,
				cpu_base_addr,
				size,
				pci_cs_windows[pci_bus][window][0],
				pci_cs_windows[pci_bus][window][1],
				pci_cs_windows[pci_bus][window][2],
				pci_cs_windows[pci_bus][window][3]);
	}

	return rc;
} /* gt64260_pci_slave_cs_set_window() */

int
gt64260_pci_slave_boot_set_window(struct pci_controller *hose,
				  u32 pci_base_addr,
				  u32 cpu_base_addr,
				  u32 size)
{
	int	rc;

	rc = gt64260_pci_slave_set_window(hose,
					  pci_base_addr,
					  cpu_base_addr,
					  size,
					  1,
					  0x20,
					  GT64260_PCI_1_SLAVE_BOOT_SIZE,
					  GT64260_PCI_1_SLAVE_BOOT_REMAP);

	return rc;
} /* gt64260_pci_slave_boot_set_window() */

int
gt64260_pci_slave_p2p_mem_set_window(struct pci_controller *hose,
				     u32 window,
				     u32 pci_base_addr,
				     u32 other_bus_base_addr,
				     u32 size)
{
	static u32
	pci_p2p_mem_windows[GT64260_PCI_BUSES][GT64260_PCI_P2P_MEM_WINDOWS][4]={
		{ /* PCI 0 */
			{ 2, 0x10,
			  GT64260_PCI_0_SLAVE_P2P_MEM_0_SIZE,
			  GT64260_PCI_0_SLAVE_P2P_MEM_0_REMAP_LO },
			{ 2, 0x14,
			  GT64260_PCI_0_SLAVE_P2P_MEM_1_SIZE,
			  GT64260_PCI_0_SLAVE_P2P_MEM_1_REMAP_LO },
		},
		{ /* PCI 1 */
			{ 2, 0x10,
			  GT64260_PCI_1_SLAVE_P2P_MEM_0_SIZE,
			  GT64260_PCI_1_SLAVE_P2P_MEM_0_REMAP_LO },
			{ 2, 0x14,
			  GT64260_PCI_1_SLAVE_P2P_MEM_1_SIZE,
			  GT64260_PCI_1_SLAVE_P2P_MEM_1_REMAP_LO },
		}
	}; /* pci_p2p_mem_windows[][][] */
	int	pci_bus;
	int	rc = -1;

	if (window < GT64260_PCI_P2P_MEM_WINDOWS) {
		pci_bus = (hose->first_busno == 0) ? 0 : 1;