irq.c

来自「Linux Kernel 2.6.9 for OMAP1710」· C语言 代码 · 共 918 行 · 第 1/2 页

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/* *	linux/arch/x86_64/kernel/irq.c * *	Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar * * This file contains the code used by various IRQ handling routines: * asking for different IRQ's should be done through these routines * instead of just grabbing them. Thus setups with different IRQ numbers * shouldn't result in any weird surprises, and installing new handlers * should be easier. *//* * (mostly architecture independent, will move to kernel/irq.c in 2.5.) * * IRQs are in fact implemented a bit like signal handlers for the kernel. * Naturally it's not a 1:1 relation, but there are similarities. */#include <linux/config.h>#include <linux/errno.h>#include <linux/module.h>#include <linux/signal.h>#include <linux/sched.h>#include <linux/ioport.h>#include <linux/interrupt.h>#include <linux/timex.h>#include <linux/slab.h>#include <linux/random.h>#include <linux/smp_lock.h>#include <linux/init.h>#include <linux/kernel_stat.h>#include <linux/irq.h>#include <linux/proc_fs.h>#include <linux/seq_file.h>#include <asm/atomic.h>#include <asm/io.h>#include <asm/smp.h>#include <asm/system.h>#include <asm/bitops.h>#include <asm/uaccess.h>#include <asm/pgalloc.h>#include <asm/delay.h>#include <asm/desc.h>#include <asm/irq.h>/* * Linux has a controller-independent x86 interrupt architecture. * every controller has a 'controller-template', that is used * by the main code to do the right thing. Each driver-visible * interrupt source is transparently wired to the appropriate * controller. Thus drivers need not be aware of the * interrupt-controller. * * Various interrupt controllers we handle: 8259 PIC, SMP IO-APIC, * PIIX4's internal 8259 PIC and SGI's Visual Workstation Cobalt (IO-)APIC. * (IO-APICs assumed to be messaging to Pentium local-APICs) * * the code is designed to be easily extended with new/different * interrupt controllers, without having to do assembly magic. *//* * Controller mappings for all interrupt sources: */irq_desc_t irq_desc[NR_IRQS] __cacheline_aligned = {	[0 ... NR_IRQS-1] = {		.handler = &no_irq_type,		.lock = SPIN_LOCK_UNLOCKED	}};static void register_irq_proc (unsigned int irq);/* * Special irq handlers. */irqreturn_t no_action(int cpl, void *dev_id, struct pt_regs *regs) { return IRQ_NONE; }/* * Generic no controller code */static void enable_none(unsigned int irq) { }static unsigned int startup_none(unsigned int irq) { return 0; }static void disable_none(unsigned int irq) { }static void ack_none(unsigned int irq){/* * 'what should we do if we get a hw irq event on an illegal vector'. * each architecture has to answer this themselves, it doesn't deserve * a generic callback i think. */#ifdef CONFIG_X86	printk("unexpected IRQ trap at vector %02x\n", irq);#ifdef CONFIG_X86_LOCAL_APIC	/*	 * Currently unexpected vectors happen only on SMP and APIC.	 * We _must_ ack these because every local APIC has only N	 * irq slots per priority level, and a 'hanging, unacked' IRQ	 * holds up an irq slot - in excessive cases (when multiple	 * unexpected vectors occur) that might lock up the APIC	 * completely.	 */	ack_APIC_irq();#endif#endif}/* startup is the same as "enable", shutdown is same as "disable" */#define shutdown_none	disable_none#define end_none	enable_nonestruct hw_interrupt_type no_irq_type = {	"none",	startup_none,	shutdown_none,	enable_none,	disable_none,	ack_none,	end_none};atomic_t irq_err_count;#ifdef CONFIG_X86_IO_APIC#ifdef APIC_MISMATCH_DEBUGatomic_t irq_mis_count;#endif#endif/* * Generic, controller-independent functions: */int show_interrupts(struct seq_file *p, void *v){	int i = *(loff_t *) v, j;	struct irqaction * action;	unsigned long flags;	if (i == 0) {		seq_printf(p, "           ");		for (j=0; j<NR_CPUS; j++)			if (cpu_online(j))				seq_printf(p, "CPU%d       ",j);		seq_putc(p, '\n');	}	if (i < NR_IRQS) {		spin_lock_irqsave(&irq_desc[i].lock, flags);		action = irq_desc[i].action;		if (!action) 			goto skip;		seq_printf(p, "%3d: ",i);#ifndef CONFIG_SMP		seq_printf(p, "%10u ", kstat_irqs(i));#else		for (j=0; j<NR_CPUS; j++)			if (cpu_online(j))			seq_printf(p, "%10u ",				kstat_cpu(j).irqs[i]);#endif		seq_printf(p, " %14s", irq_desc[i].handler->typename);		seq_printf(p, "  %s", action->name);		for (action=action->next; action; action = action->next)			seq_printf(p, ", %s", action->name);		seq_putc(p, '\n');skip:		spin_unlock_irqrestore(&irq_desc[i].lock, flags);	} else if (i == NR_IRQS) {		seq_printf(p, "NMI: ");		for (j = 0; j < NR_CPUS; j++)			if (cpu_online(j))				seq_printf(p, "%10u ", cpu_pda[j].__nmi_count);		seq_putc(p, '\n');#ifdef CONFIG_X86_LOCAL_APIC		seq_printf(p, "LOC: ");		for (j = 0; j < NR_CPUS; j++)			if (cpu_online(j))				seq_printf(p, "%10u ", cpu_pda[j].apic_timer_irqs);		seq_putc(p, '\n');#endif		seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count));#ifdef CONFIG_X86_IO_APIC#ifdef APIC_MISMATCH_DEBUG		seq_printf(p, "MIS: %10u\n", atomic_read(&irq_mis_count));#endif#endif	}	return 0;}#ifdef CONFIG_SMPinline void synchronize_irq(unsigned int irq){	while (irq_desc[irq].status & IRQ_INPROGRESS)		cpu_relax();}#endif/* * This should really return information about whether * we should do bottom half handling etc. Right now we * end up _always_ checking the bottom half, which is a * waste of time and is not what some drivers would * prefer. */int handle_IRQ_event(unsigned int irq, struct pt_regs * regs, struct irqaction * action){	int status = 1; /* Force the "do bottom halves" bit */	int ret;	if (!(action->flags & SA_INTERRUPT))		local_irq_enable();	do {		ret = action->handler(irq, action->dev_id, regs);		if (ret == IRQ_HANDLED)			status |= action->flags;		action = action->next;	} while (action);	if (status & SA_SAMPLE_RANDOM)		add_interrupt_randomness(irq);	local_irq_disable();	return status;}/* * Generic enable/disable code: this just calls * down into the PIC-specific version for the actual * hardware disable after having gotten the irq * controller lock.  */ /** *	disable_irq_nosync - disable an irq without waiting *	@irq: Interrupt to disable * *	Disable the selected interrupt line.  Disables and Enables are *	nested. *	Unlike disable_irq(), this function does not ensure existing *	instances of the IRQ handler have completed before returning. * *	This function must not be called from IRQ context. */ inline void disable_irq_nosync(unsigned int irq){	irq_desc_t *desc = irq_desc + irq;	unsigned long flags;	spin_lock_irqsave(&desc->lock, flags);	if (!desc->depth++) {		desc->status |= IRQ_DISABLED;		desc->handler->disable(irq);	}	spin_unlock_irqrestore(&desc->lock, flags);}/** *	disable_irq - disable an irq and wait for completion *	@irq: Interrupt to disable * *	Disable the selected interrupt line.  Enables and Disables are *	nested. *	This function waits for any pending IRQ handlers for this interrupt *	to complete before returning. If you use this function while *	holding a resource the IRQ handler may need you will deadlock. * *	This function may be called - with care - from IRQ context. */ void disable_irq(unsigned int irq){	disable_irq_nosync(irq);	synchronize_irq(irq);}/** *	enable_irq - enable handling of an irq *	@irq: Interrupt to enable * *	Undoes the effect of one call to disable_irq().  If this *	matches the last disable, processing of interrupts on this *	IRQ line is re-enabled. * *	This function may be called from IRQ context. */ void enable_irq(unsigned int irq){	irq_desc_t *desc = irq_desc + irq;	unsigned long flags;	spin_lock_irqsave(&desc->lock, flags);	switch (desc->depth) {	case 1: {		unsigned int status = desc->status & ~IRQ_DISABLED;		desc->status = status;		if ((status & (IRQ_PENDING | IRQ_REPLAY)) == IRQ_PENDING) {			desc->status = status | IRQ_REPLAY;			hw_resend_irq(desc->handler,irq);		}		desc->handler->enable(irq);		/* fall-through */	}	default:		desc->depth--;		break;	case 0:		printk("enable_irq(%u) unbalanced from %p\n", irq,		       __builtin_return_address(0));	}	spin_unlock_irqrestore(&desc->lock, flags);}/* * do_IRQ handles all normal device IRQ's (the special * SMP cross-CPU interrupts have their own specific * handlers). */asmlinkage unsigned int do_IRQ(struct pt_regs *regs){		/* 	 * We ack quickly, we don't want the irq controller	 * thinking we're snobs just because some other CPU has	 * disabled global interrupts (we have already done the	 * INT_ACK cycles, it's too late to try to pretend to the	 * controller that we aren't taking the interrupt).	 *	 * 0 return value means that this irq is already being	 * handled by some other CPU. (or is disabled)	 */	unsigned irq = regs->orig_rax & 0xff; /* high bits used in ret_from_ code  */	int cpu = smp_processor_id();	irq_desc_t *desc = irq_desc + irq;	struct irqaction * action;	unsigned int status;	if (irq > 256) BUG();	irq_enter(); 	kstat_cpu(cpu).irqs[irq]++;	spin_lock(&desc->lock);	desc->handler->ack(irq);	/*	   REPLAY is when Linux resends an IRQ that was dropped earlier	   WAITING is used by probe to mark irqs that are being tested	   */	status = desc->status & ~(IRQ_REPLAY | IRQ_WAITING);	status |= IRQ_PENDING; /* we _want_ to handle it */	/*	 * If the IRQ is disabled for whatever reason, we cannot	 * use the action we have.	 */	action = NULL;	if (likely(!(status & (IRQ_DISABLED | IRQ_INPROGRESS)))) {		action = desc->action;		status &= ~IRQ_PENDING; /* we commit to handling */		status |= IRQ_INPROGRESS; /* we are handling it */	}	desc->status = status;	/*	 * If there is no IRQ handler or it was disabled, exit early.	   Since we set PENDING, if another processor is handling	   a different instance of this same irq, the other processor	   will take care of it.	 */	if (unlikely(!action))		goto out;	/*	 * Edge triggered interrupts need to remember	 * pending events.	 * This applies to any hw interrupts that allow a second	 * instance of the same irq to arrive while we are in do_IRQ	 * or in the handler. But the code here only handles the _second_	 * instance of the irq, not the third or fourth. So it is mostly	 * useful for irq hardware that does not mask cleanly in an	 * SMP environment.	 */	for (;;) {		spin_unlock(&desc->lock);		handle_IRQ_event(irq, regs, action);		spin_lock(&desc->lock);				if (unlikely(!(desc->status & IRQ_PENDING)))			break;		desc->status &= ~IRQ_PENDING;	}	desc->status &= ~IRQ_INPROGRESS;out:	/*	 * The ->end() handler has to deal with interrupts which got	 * disabled while the handler was running.	 */	if (irq > 256) BUG();	desc->handler->end(irq);	spin_unlock(&desc->lock);	irq_exit();	return 1;}int can_request_irq(unsigned int irq, unsigned long irqflags){	struct irqaction *action;	if (irq >= NR_IRQS)		return 0;	action = irq_desc[irq].action;	if (action) {		if (irqflags & action->flags & SA_SHIRQ)			action = NULL;	}	return !action;}/** *	request_irq - allocate an interrupt line *	@irq: Interrupt line to allocate *	@handler: Function to be called when the IRQ occurs *	@irqflags: Interrupt type flags *	@devname: An ascii name for the claiming device *	@dev_id: A cookie passed back to the handler function * *	This call allocates interrupt resources and enables the *	interrupt line and IRQ handling. From the point this *	call is made your handler function may be invoked. Since *	your handler function must clear any interrupt the board  *	raises, you must take care both to initialise your hardware *	and to set up the interrupt handler in the right order. * *	Dev_id must be globally unique. Normally the address of the *	device data structure is used as the cookie. Since the handler *	receives this value it makes sense to use it. * *	If your interrupt is shared you must pass a non NULL dev_id *	as this is required when freeing the interrupt. * *	Flags: * *	SA_SHIRQ		Interrupt is shared * *	SA_INTERRUPT		Disable local interrupts while processing * *	SA_SAMPLE_RANDOM	The interrupt can be used for entropy * */ int request_irq(unsigned int irq, 

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