core.c

来自「Linux Kernel 2.6.9 for OMAP1710」· C语言 代码 · 共 222 行

/* 
 * linux/arch/arm/mach-omap2/core.c
 * 
 * Basic initalization of the platform
 *
 * Copyright (C) 2004 Texas Instruments, Inc. 
 * 
 * This package is free software; you can redistribute it and/or modify 
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation. 
 * 
 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR 
 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED 
 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. 
 */

#include <linux/config.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/device.h>
#include <linux/slab.h>
#include <linux/string.h>

#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/arch/irqs.h>
#include <asm/setup.h>
#include <asm/mach-types.h>

#include <asm/mach/arch.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>

#include <asm/arch/platform.h>
#include <asm/arch/dma.h>
#include <asm/arch/eac.h>
#include <asm/arch/sys_info.h>

#undef	DEBUG_24XX

static struct resource smc91x_resources[] = {
	[0] = {
	       .start = OMAP24xx_ETHR_BASE,	/* Physical */
	       .end = OMAP24xx_ETHR_BASE + SZ_4K,
	       .flags = IORESOURCE_MEM,
	       },
	[1] = {
	       .start = 0,	/* Really GPIO 0  */
	       .end = 0,
	       .flags = IORESOURCE_IRQ,
	       },
};

static struct platform_device smc91x_device = {
	.name = "smc91x",
	.id = 0,
	.num_resources = ARRAY_SIZE(smc91x_resources),
	.resource = smc91x_resources,
};
static struct platform_device *devices[] __initdata = {
	&smc91x_device,
};

static void omap24xx_init(void)
{
	(void)platform_add_devices(devices, ARRAY_SIZE(devices));
}

static struct map_desc omap24xx_io_desc[] __initdata = {
	{IO_VIRT_L4, OMAP24XX_L4_IO_BASE, IO_SIZE_L4, MT_DEVICE},
	{IO_VIRT_L3, OMAP24XX_L3_IO_BASE, IO_SIZE_L3, MT_DEVICE},
	{H4_DEBUG_FPGA_VA_BASE, H4_DEBUG_FPGA_BASE, SZ_4K, MT_DEVICE},
};

static void __init omap24xx_map_io(void)
{
	iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
	display_board_info();
}

#define ALLPCI ( (1 << IRQ_PCIINT0) | (1 << IRQ_PCIINT1) | (1 << IRQ_PCIINT2) | (1 << IRQ_PCIINT3) )

u32 omap_ih_base[] =
    { OMAP24XX_IH_0_BASE, OMAP24XX_IH_1_BASE, OMAP24XX_IH_2_BASE };

static inline void write_ih(int part, int reg, u32 val)
{
	int dv = 0;
	__asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4"::"r"(dv));	/* memory barrier */
	writel(val, omap_ih_base[part] + reg);
	__asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4"::"r"(dv));	/* memory barrier */
}

inline u32 read_ih(int part, int reg)
{
	int dv = 0;
	__asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4"::"r"(dv));	/* memory barrier */
	return readl(omap_ih_base[part] + reg);
	__asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4"::"r"(dv));	/* memory barrier */
}

static inline int get_part(int irq)
{
	return (irq >> 5);
}

static void sc_mask_irq(unsigned int irq)
{
	u32 mask;
	int part = get_part(irq);
	if (irq >= 64)
		irq = irq % 64;
	else if (irq >= 32)
		irq = irq % 32;

	mask = (1 << irq);
	write_ih(part, IRQ_MIR_SET, mask);
}

static void sc_unmask_irq(unsigned int irq)
{
	u32 mask;
	int part = get_part(irq);
	if (irq >= 64)
		irq = irq % 64;
	else if (irq >= 32)
		irq = irq % 32;
	mask = (1 << irq);
	write_ih(part, IRQ_MIR_CLEAR, mask);
}
static void sc_ack_irq(unsigned int irq)
{
	int val = 0;
#ifdef	DEBUG_24XX
	printk("\nBEFORE  SIR_IRQ = %x, ITR1 = %x , PENDIG_IRQ1 = %x \n",
	       readl(OMAP24XX_IH_BASE + IRQ_SIR_IRQ),
	       readl(OMAP24XX_IH_1_BASE + IRQ_ITR),
	       readl(OMAP24XX_IH_1_BASE + IRQ_PENDING_IRQ));
#endif
	writel(0x0, OMAP24XX_IH_0_BASE + IRQ_ITR);	/* itr's are read only registers */
	writel(0x0, OMAP24XX_IH_1_BASE + IRQ_ITR);
	writel(0x0, OMAP24XX_IH_2_BASE + IRQ_ITR);
	__asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4"::"r"(val));	/* memory barrier */
	writel(0x1, OMAP24XX_IH_BASE + IRQ_CONTROL_REG);	//ack irq allow another (masked above)
	__asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4"::"r"(val));	/* memory barrier */
#ifdef  DEBUG_24XX
	printk("\n timer acked");
	printk("\nAFTER SIR_IRQ = %x, ITR1 = %x , PENDIG_IRQ1 = %x ",
	       readl(OMAP24XX_IH_BASE + IRQ_SIR_IRQ), i
	       readl(OMAP24XX_IH_1_BASE + IRQ_ITR),
	       readl(OMAP24XX_IH_1_BASE + IRQ_PENDING_IRQ));
#endif
}

static void sc_mask_ack_irq(unsigned int irq)
{
	sc_mask_irq(irq);
	sc_ack_irq(irq);
}

static struct irqchip sc_chip = {
	.ack = sc_mask_ack_irq,
	.mask = sc_mask_irq,
	.unmask = sc_unmask_irq,
};

static void __init omap24xx_init_irq(void)
{
	int temp;
	unsigned int i;

	/* Disable all interrupts initially. */
	/* Do the core module ones */

#ifdef  DEBUG_24XX
	printk("\n resetting the interrupt controller");
#endif

	writel(0x2, OMAP24XX_IH_BASE + 0x10);
	temp = readl(OMAP24XX_IH_BASE + 0x14);

#ifdef  DEBUG_24XX
	printk("\n reset status = %x", temp);
#endif

	for (i = 0; i < 3; i++) {
		write_ih(i, IRQ_MIR_SET, ~0x0);
		write_ih(i, IRQ_ITR, 0x0);
	}
	writel(3, OMAP24XX_IH_BASE + IRQ_CONTROL_REG);
	for (i = 0; i < CPU_LAST; i++) {
		set_irq_chip(i, &sc_chip);
		set_irq_handler(i, do_level_IRQ);
		set_irq_flags(i, IRQF_VALID);
		/* setting level interrupts in ILR */
		writel(0x02, OMAP24XX_ILR_BASE + (i * 4));
	}
}

static void __init
fixup_omap24xx(struct machine_desc *desc, struct tag *tags,
	       char **cmdline, struct meminfo *mi)
{
	return;
}

extern void omap24xx_time_init(void);

MACHINE_START(OMAP_H4, "OMAP24xx H4")
MAINTAINER("Texas Instruments Inc.")
BOOT_MEM(OMAP2420_SDRC_CS0, OMAP24XX_L4_IO_BASE, IO_VIRT_L4)
BOOT_PARAMS((OMAP2420_SDRC_CS0 + 0x100))
MAPIO(omap24xx_map_io)
INITIRQ(omap24xx_init_irq)
FIXUP(fixup_omap24xx)
INIT_MACHINE(omap24xx_init)
INITTIME(omap24xx_time_init)
MACHINE_END