pcibr_reg.c

来自「Linux Kernel 2.6.9 for OMAP1710」· C语言 代码 · 共 880 行 · 第 1/2 页

}

void
pcireg_intr_enable_set(pcibr_soft_t ptr, uint64_t val)
{
	pic_t *bridge = (pic_t *)ptr->bs_base;

	bridge->p_int_enable = val;
}

void
pcireg_intr_enable_bit_clr(pcibr_soft_t ptr, uint64_t bits)
{
	pic_t *bridge = (pic_t *)ptr->bs_base;

	bridge->p_int_enable &= ~bits;
}

void
pcireg_intr_enable_bit_set(pcibr_soft_t ptr, uint64_t bits)
{
	pic_t *bridge = (pic_t *)ptr->bs_base;

	bridge->p_int_enable |= bits;
}

/*
 * Interrupt Reset Register Access -- Write Only		    0000_0110
 */
void
pcireg_intr_reset_set(pcibr_soft_t ptr, uint64_t val)
{
	pic_t *bridge = (pic_t *)ptr->bs_base;

	bridge->p_int_rst_stat = val;
}

void
pcireg_intr_mode_set(pcibr_soft_t ptr, uint64_t val)
{
	pic_t *bridge = (pic_t *)ptr->bs_base;

	bridge->p_int_mode = val;
}

void
pcireg_intr_device_set(pcibr_soft_t ptr, uint64_t val)
{
	pic_t *bridge = (pic_t *)ptr->bs_base;

	bridge->p_int_device = val;
}

static void
__pcireg_intr_device_bit_set(pic_t *bridge, uint64_t bits)
{
	bridge->p_int_device |= bits;
}

void
pcireg_bridge_intr_device_bit_set(void *ptr, uint64_t bits)
{
	__pcireg_intr_device_bit_set((pic_t *)ptr, bits);
}

void
pcireg_intr_device_bit_set(pcibr_soft_t ptr, uint64_t bits)
{
	__pcireg_intr_device_bit_set((pic_t *)ptr->bs_base, bits);
}

void
pcireg_intr_device_bit_clr(pcibr_soft_t ptr, uint64_t bits)
{
	pic_t *bridge = (pic_t *)ptr->bs_base;

	bridge->p_int_device &= ~bits;
}

/*
 * Host Error Interrupt Field Register Access -- Read/Write	    0000_0128
 */
void
pcireg_intr_host_err_set(pcibr_soft_t ptr, uint64_t val)
{
	pic_t *bridge = (pic_t *)ptr->bs_base;

	bridge->p_int_host_err = val;
}

/*
 * Interrupt Host Address Register -- Read/Write	0000_0130 - 0000_0168
 */
uint64_t
pcireg_intr_addr_get(pcibr_soft_t ptr, int int_n)
{
	pic_t *bridge = (pic_t *)ptr->bs_base;

	return bridge->p_int_addr[int_n];
}

static void
__pcireg_intr_addr_set(pic_t *bridge, int int_n, uint64_t val)
{
	bridge->p_int_addr[int_n] = val;
}

void
pcireg_bridge_intr_addr_set(void *ptr, int int_n, uint64_t val)
{
	__pcireg_intr_addr_set((pic_t *)ptr, int_n, val);
}

void
pcireg_intr_addr_set(pcibr_soft_t ptr, int int_n, uint64_t val)
{
	__pcireg_intr_addr_set((pic_t *)ptr->bs_base, int_n, val);
}

void *
pcireg_intr_addr_addr(pcibr_soft_t ptr, int int_n)
{
	pic_t *bridge = (pic_t *)ptr->bs_base;

	return (void *)&(bridge->p_int_addr[int_n]);
}

static void
__pcireg_intr_addr_vect_set(pic_t *bridge, int int_n, uint64_t vect)
{
	bridge->p_int_addr[int_n] &= ~PIC_HOST_INTR_FLD;
	bridge->p_int_addr[int_n] |=
		    ((vect << PIC_HOST_INTR_FLD_SHFT) & PIC_HOST_INTR_FLD);
}

void
pcireg_bridge_intr_addr_vect_set(void *ptr, int int_n, uint64_t vect)
{
	__pcireg_intr_addr_vect_set((pic_t *)ptr, int_n, vect);
}

void
pcireg_intr_addr_vect_set(pcibr_soft_t ptr, int int_n, uint64_t vect)
{
	__pcireg_intr_addr_vect_set((pic_t *)ptr->bs_base, int_n, vect);
}



/*
 * Intr Host Address Register (int_addr) -- Read/Write	0000_0130 - 0000_0168
 */
static void
__pcireg_intr_addr_addr_set(pic_t *bridge, int int_n, uint64_t addr)
{
	bridge->p_int_addr[int_n] &= ~PIC_HOST_INTR_ADDR;
	bridge->p_int_addr[int_n] |= (addr & PIC_HOST_INTR_ADDR);
}

void
pcireg_bridge_intr_addr_addr_set(void *ptr, int int_n, uint64_t addr)
{
	__pcireg_intr_addr_addr_set((pic_t *)ptr, int_n, addr);
}

void
pcireg_intr_addr_addr_set(pcibr_soft_t ptr, int int_n, uint64_t addr)
{
	__pcireg_intr_addr_addr_set((pic_t *)ptr->bs_base, int_n, addr);
}

/*
 * Multiple Interrupt Register Access -- Read Only		    0000_0178
 */
uint64_t
pcireg_intr_multiple_get(pcibr_soft_t ptr)
{
	pic_t *bridge = (pic_t *)ptr->bs_base;

	return bridge->p_mult_int;
}

/*
 * Force Always Intr Register Access -- Write Only	0000_0180 - 0000_01B8
 */
static void *
__pcireg_force_always_addr_get(pic_t *bridge, int int_n)
{
	return (void *)&(bridge->p_force_always[int_n]);
}

void *
pcireg_bridge_force_always_addr_get(void *ptr, int int_n)
{
	return __pcireg_force_always_addr_get((pic_t *)ptr, int_n);
}

void *
pcireg_force_always_addr_get(pcibr_soft_t ptr, int int_n)
{
	return __pcireg_force_always_addr_get((pic_t *)ptr->bs_base, int_n);
}

/*
 * Force Interrupt Register Access -- Write Only	0000_01C0 - 0000_01F8
 */
void
pcireg_force_intr_set(pcibr_soft_t ptr, int int_n)
{
	pic_t *bridge = (pic_t *)ptr->bs_base;

	bridge->p_force_pin[int_n] = 1;
}

/*
 * Device(x) Register Access -- Read/Write		0000_0200 - 0000_0218
 */
uint64_t
pcireg_device_get(pcibr_soft_t ptr, int device)
{
	pic_t *bridge = (pic_t *)ptr->bs_base;

	ASSERT_ALWAYS((device >= 0) && (device <= 3));
	return bridge->p_device[device];
}

void
pcireg_device_set(pcibr_soft_t ptr, int device, uint64_t val)
{
	pic_t *bridge = (pic_t *)ptr->bs_base;

	ASSERT_ALWAYS((device >= 0) && (device <= 3));
	bridge->p_device[device] = val;
}

/*
 * Device(x) Write Buffer Flush Reg Access -- Read Only	0000_0240 - 0000_0258
 */
uint64_t
pcireg_wrb_flush_get(pcibr_soft_t ptr, int device)
{
	pic_t *bridge = (pic_t *)ptr->bs_base;
	uint64_t ret = 0;

	ASSERT_ALWAYS((device >= 0) && (device <= 3));
	ret = bridge->p_wr_req_buf[device];

	/* Read of the Write Buffer Flush should always return zero */
	ASSERT_ALWAYS(ret == 0);
	return ret;
}

/*
 * Even/Odd RRB Register Access -- Read/Write		0000_0280 - 0000_0288
 */
uint64_t
pcireg_rrb_get(pcibr_soft_t ptr, int even_odd)
{
	pic_t *bridge = (pic_t *)ptr->bs_base;

	return bridge->p_rrb_map[even_odd];
}

void
pcireg_rrb_set(pcibr_soft_t ptr, int even_odd, uint64_t val)
{
	pic_t *bridge = (pic_t *)ptr->bs_base;

	bridge->p_rrb_map[even_odd] = val;
}

void
pcireg_rrb_bit_set(pcibr_soft_t ptr, int even_odd, uint64_t bits)
{
	pic_t *bridge = (pic_t *)ptr->bs_base;

	bridge->p_rrb_map[even_odd] |= bits;
}

/*
 * RRB Status Register Access -- Read Only			    0000_0290
 */
uint64_t
pcireg_rrb_status_get(pcibr_soft_t ptr)
{
	pic_t *bridge = (pic_t *)ptr->bs_base;

	return bridge->p_resp_status;
}

/*
 * RRB Clear Register Access -- Write Only			    0000_0298
 */
void
pcireg_rrb_clear_set(pcibr_soft_t ptr, uint64_t val)
{
	pic_t *bridge = (pic_t *)ptr->bs_base;

	bridge->p_resp_clear = val;
}

/*
 * PCIX Bus Error Address Register Access -- Read Only		    0000_0600
 */
uint64_t
pcireg_pcix_bus_err_addr_get(pcibr_soft_t ptr)
{
	pic_t *bridge = (pic_t *)ptr->bs_base;

	return bridge->p_pcix_bus_err_addr;
}

/*
 * PCIX Bus Error Attribute Register Access -- Read Only	    0000_0608
 */
uint64_t
pcireg_pcix_bus_err_attr_get(pcibr_soft_t ptr)
{
	pic_t *bridge = (pic_t *)ptr->bs_base;

	return bridge->p_pcix_bus_err_attr;
}

/*
 * PCIX Bus Error Data Register Access -- Read Only		    0000_0610
 */
uint64_t
pcireg_pcix_bus_err_data_get(pcibr_soft_t ptr)
{
	pic_t *bridge = (pic_t *)ptr->bs_base;

	return bridge->p_pcix_bus_err_data;
}

/*
 * PCIX PIO Split Request Address Register Access -- Read Only	    0000_0618
 */
uint64_t
pcireg_pcix_pio_split_addr_get(pcibr_soft_t ptr)
{
	pic_t *bridge = (pic_t *)ptr->bs_base;

	return bridge->p_pcix_pio_split_addr;
}

/*
 * PCIX PIO Split Request Attribute Register Access -- Read Only    0000_0620
 */
uint64_t
pcireg_pcix_pio_split_attr_get(pcibr_soft_t ptr)
{
	pic_t *bridge = (pic_t *)ptr->bs_base;

	return bridge->p_pcix_pio_split_attr;
}

/*
 * PCIX DMA Request Error Attribute Register Access -- Read Only    0000_0628
 */
uint64_t
pcireg_pcix_req_err_attr_get(pcibr_soft_t ptr)
{
	pic_t *bridge = (pic_t *)ptr->bs_base;

	return bridge->p_pcix_dma_req_err_attr;
}

/*
 * PCIX DMA Request Error Address Register Access -- Read Only	    0000_0630
 */
uint64_t
pcireg_pcix_req_err_addr_get(pcibr_soft_t ptr)
{
	pic_t *bridge = (pic_t *)ptr->bs_base;

	return bridge->p_pcix_dma_req_err_addr;
}

/*
 * Type 0 Configuration Space Access -- Read/Write
 */
cfg_p
pcireg_type0_cfg_addr(pcibr_soft_t ptr, uint8_t slot, uint8_t func, int off)
{
	pic_t *bridge = (pic_t *)ptr->bs_base;

	/* Type 0 Config space accesses on PIC are 1-4, not 0-3 since
	 * it is a PCIX Bridge.  See sys/PCI/pic.h for explanation.
	 */
	slot++;
	ASSERT_ALWAYS(((int) slot >= 1) && ((int) slot <= 4));
	return &(bridge->p_type0_cfg_dev[slot].f[func].l[(off / 4)]);
}

/*
 * Type 1 Configuration Space Access -- Read/Write
 */
cfg_p
pcireg_type1_cfg_addr(pcibr_soft_t ptr, uint8_t func, int offset)
{
	pic_t *bridge = (pic_t *)ptr->bs_base;

	/*
	 * Return a config space address for the given slot/func/offset.
	 * Note the returned ptr is a 32bit word (ie. cfg_p) aligned ptr
	 * pointing to the 32bit word that contains the "offset" byte.
	 */
	return &(bridge->p_type1_cfg.f[func].l[(offset / 4)]);
}

/*
 * Internal ATE SSRAM Access -- Read/Write 
 */
bridge_ate_t
pcireg_int_ate_get(pcibr_soft_t ptr, int ate_index)
{
	pic_t *bridge = (pic_t *)ptr->bs_base;

	ASSERT_ALWAYS((ate_index >= 0) && (ate_index <= 1024));
	return bridge->p_int_ate_ram[ate_index];
}

void
pcireg_int_ate_set(pcibr_soft_t ptr, int ate_index, bridge_ate_t val)
{
	pic_t *bridge = (pic_t *)ptr->bs_base;

	ASSERT_ALWAYS((ate_index >= 0) && (ate_index <= 1024));
	bridge->p_int_ate_ram[ate_index] = (picate_t) val;
}

bridge_ate_p
pcireg_int_ate_addr(pcibr_soft_t ptr, int ate_index)
{
	pic_t *bridge = (pic_t *)ptr->bs_base;

	ASSERT_ALWAYS((ate_index >= 0) && (ate_index <= 1024));
	return &(bridge->p_int_ate_ram[ate_index]);
}