toshiba_rbtx4927_setup.c

Linux Kernel 2.6.9 for OMAP1710

						pci_devfn, 0xb0, &v32_b0);
			early_read_config_byte(hose, busno, busno,
					       pci_devfn, 0xe1, &v08_e1);

			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
			     ":%s beg 0x64 = 0x%02x\n", s, v08_64);
			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
			     ":%s beg 0xb0 = 0x%02x\n", s, v32_b0);
			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
			     ":%s beg 0xe1 = 0x%02x\n", s, v08_e1);

			/* serial irq control */
			v08_64 = 0xd0;

			/* serial irq pin */
			v32_b0 |= 0x00010000;

			/* ide irq on isa14 */
			v08_e1 &= 0xf0;
			v08_e1 |= 0x0d;

			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
			     ":%s mid 0x64 = 0x%02x\n", s, v08_64);
			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
			     ":%s mid 0xb0 = 0x%02x\n", s, v32_b0);
			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
			     ":%s mid 0xe1 = 0x%02x\n", s, v08_e1);

			early_write_config_byte(hose, busno, busno,
						pci_devfn, 0x64, v08_64);
			early_write_config_dword(hose, busno, busno,
						 pci_devfn, 0xb0, v32_b0);
			early_write_config_byte(hose, busno, busno,
						pci_devfn, 0xe1, v08_e1);

#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
			{
				early_read_config_byte(hose, busno, busno,
						       pci_devfn, 0x64,
						       &v08_64);
				early_read_config_dword(hose, busno, busno,
							pci_devfn, 0xb0,
							&v32_b0);
				early_read_config_byte(hose, busno, busno,
						       pci_devfn, 0xe1,
						       &v08_e1);

				TOSHIBA_RBTX4927_SETUP_DPRINTK
				    (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
				     ":%s end 0x64 = 0x%02x\n", s, v08_64);
				TOSHIBA_RBTX4927_SETUP_DPRINTK
				    (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
				     ":%s end 0xb0 = 0x%02x\n", s, v32_b0);
				TOSHIBA_RBTX4927_SETUP_DPRINTK
				    (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
				     ":%s end 0xe1 = 0x%02x\n", s, v08_e1);
			}
#endif

			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n",
			     s);
		}

		if (id == 0x91301055) {
			u8 v08_04;
			u8 v08_09;
			u8 v08_41;
			u8 v08_43;
			u8 v08_5c;
			char *s = " sb/ide --";

			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n",
			     s);

			early_read_config_byte(hose, busno, busno,
					       pci_devfn, 0x04, &v08_04);
			early_read_config_byte(hose, busno, busno,
					       pci_devfn, 0x09, &v08_09);
			early_read_config_byte(hose, busno, busno,
					       pci_devfn, 0x41, &v08_41);
			early_read_config_byte(hose, busno, busno,
					       pci_devfn, 0x43, &v08_43);
			early_read_config_byte(hose, busno, busno,
					       pci_devfn, 0x5c, &v08_5c);

			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
			     ":%s beg 0x04 = 0x%02x\n", s, v08_04);
			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
			     ":%s beg 0x09 = 0x%02x\n", s, v08_09);
			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
			     ":%s beg 0x41 = 0x%02x\n", s, v08_41);
			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
			     ":%s beg 0x43 = 0x%02x\n", s, v08_43);
			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
			     ":%s beg 0x5c = 0x%02x\n", s, v08_5c);

			/* enable ide master/io */
			v08_04 |= (PCI_COMMAND_MASTER | PCI_COMMAND_IO);

			/* enable ide native mode */
			v08_09 |= 0x05;

			/* enable primary ide */
			v08_41 |= 0x80;

			/* enable secondary ide */
			v08_43 |= 0x80;

			/* 
			 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
			 *
			 * This line of code is intended to provide the user with a work
			 * around solution to the anomalies cited in SMSC's anomaly sheet
			 * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"".
			 *
			 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
			 */
			v08_5c |= 0x01;

			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
			     ":%s mid 0x04 = 0x%02x\n", s, v08_04);
			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
			     ":%s mid 0x09 = 0x%02x\n", s, v08_09);
			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
			     ":%s mid 0x41 = 0x%02x\n", s, v08_41);
			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
			     ":%s mid 0x43 = 0x%02x\n", s, v08_43);
			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
			     ":%s mid 0x5c = 0x%02x\n", s, v08_5c);

			early_write_config_byte(hose, busno, busno,
						pci_devfn, 0x5c, v08_5c);
			early_write_config_byte(hose, busno, busno,
						pci_devfn, 0x04, v08_04);
			early_write_config_byte(hose, busno, busno,
						pci_devfn, 0x09, v08_09);
			early_write_config_byte(hose, busno, busno,
						pci_devfn, 0x41, v08_41);
			early_write_config_byte(hose, busno, busno,
						pci_devfn, 0x43, v08_43);

#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
			{
				early_read_config_byte(hose, busno, busno,
						       pci_devfn, 0x04,
						       &v08_04);
				early_read_config_byte(hose, busno, busno,
						       pci_devfn, 0x09,
						       &v08_09);
				early_read_config_byte(hose, busno, busno,
						       pci_devfn, 0x41,
						       &v08_41);
				early_read_config_byte(hose, busno, busno,
						       pci_devfn, 0x43,
						       &v08_43);
				early_read_config_byte(hose, busno, busno,
						       pci_devfn, 0x5c,
						       &v08_5c);

				TOSHIBA_RBTX4927_SETUP_DPRINTK
				    (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
				     ":%s end 0x04 = 0x%02x\n", s, v08_04);
				TOSHIBA_RBTX4927_SETUP_DPRINTK
				    (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
				     ":%s end 0x09 = 0x%02x\n", s, v08_09);
				TOSHIBA_RBTX4927_SETUP_DPRINTK
				    (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
				     ":%s end 0x41 = 0x%02x\n", s, v08_41);
				TOSHIBA_RBTX4927_SETUP_DPRINTK
				    (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
				     ":%s end 0x43 = 0x%02x\n", s, v08_43);
				TOSHIBA_RBTX4927_SETUP_DPRINTK
				    (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
				     ":%s end 0x5c = 0x%02x\n", s, v08_5c);
			}
#endif

			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n",
			     s);
		}

	}

	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
				       "+\n");

	return busno;
}

extern struct resource pci_io_resource;
extern struct resource pci_mem_resource;

void tx4927_pci_setup(void)
{
	static int called = 0;
	extern unsigned int tx4927_get_mem_size(void);

	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "-\n");

#ifndef  TX4927_SUPPORT_PCI_66
	if (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66)
		printk("PCI 66 current unsupported\n");
#endif

	mips_memory_upper = tx4927_get_mem_size() << 20;
	mips_memory_upper += KSEG0;
	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
				       "0x%08lx=mips_memory_upper\n",
				       mips_memory_upper);
	mips_pci_io_base = TX4927_PCIIO;
	mips_pci_io_size = TX4927_PCIIO_SIZE;
	mips_pci_mem_base = TX4927_PCIMEM;
	mips_pci_mem_size = TX4927_PCIMEM_SIZE;

	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
				       "0x%08lx=mips_pci_io_base\n",
				       mips_pci_io_base);
	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
				       "0x%08lx=mips_pci_io_size\n",
				       mips_pci_io_size);
	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
				       "0x%08lx=mips_pci_mem_base\n",
				       mips_pci_mem_base);
	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
				       "0x%08lx=mips_pci_mem_size\n",
				       mips_pci_mem_size);
	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
				       "0x%08lx=pci_io_resource.start\n",
				       pci_io_resource.start);
	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
				       "0x%08lx=pci_io_resource.end\n",
				       pci_io_resource.end);
	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
				       "0x%08lx=pci_mem_resource.start\n",
				       pci_mem_resource.start);
	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
				       "0x%08lx=pci_mem_resource.end\n",
				       pci_mem_resource.end);
	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
				       "0x%08lx=mips_io_port_base",
				       mips_io_port_base);

	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
				       "setup pci_io_resource  to 0x%08lx 0x%08lx\n",
				       pci_io_resource.start,
				       pci_io_resource.end);
	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
				       "setup pci_mem_resource to 0x%08lx 0x%08lx\n",
				       pci_mem_resource.start,
				       pci_mem_resource.end);

	if (!called) {
		printk
		    ("TX4927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
		     (unsigned short) (tx4927_pcicptr->pciid >> 16),
		     (unsigned short) (tx4927_pcicptr->pciid & 0xffff),
		     (unsigned short) (tx4927_pcicptr->pciccrev & 0xff),
		     (!(tx4927_ccfgptr->
			ccfg & TX4927_CCFG_PCIXARB)) ? "External" :
		     "Internal");
		called = 1;
	}
	printk("%s PCIC --%s PCICLK:",toshiba_name,
	       (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : "");
	if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) {
		int pciclk = 0;
		switch ((unsigned long) tx4927_ccfgptr->
			ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
		case TX4927_CCFG_PCIDIVMODE_2_5:
			pciclk = tx4927_cpu_clock * 2 / 5;
			break;
		case TX4927_CCFG_PCIDIVMODE_3:
			pciclk = tx4927_cpu_clock / 3;
			break;
		case TX4927_CCFG_PCIDIVMODE_5:
			pciclk = tx4927_cpu_clock / 5;
			break;
		case TX4927_CCFG_PCIDIVMODE_6:
			pciclk = tx4927_cpu_clock / 6;
			break;
		}
		printk("Internal(%dMHz)", pciclk / 1000000);
	} else {
		int pciclk = 0;
		int pciclk_setting = *tx4927_pci_clk_ptr;
		switch (pciclk_setting & TX4927_PCI_CLK_MASK) {
		case TX4927_PCI_CLK_33:
			pciclk = 33333333;
			break;
		case TX4927_PCI_CLK_25:
			pciclk = 25000000;
			break;
		case TX4927_PCI_CLK_66:
			pciclk = 66666666;
			break;
		case TX4927_PCI_CLK_50:
			pciclk = 50000000;
			break;
		}
		printk("External(%dMHz)", pciclk / 1000000);
	}
	printk("\n");



	/* GB->PCI mappings */
	tx4927_pcicptr->g2piomask = (mips_pci_io_size - 1) >> 4;
	tx4927_pcicptr->g2piogbase = mips_pci_io_base |
#ifdef __BIG_ENDIAN
	    TX4927_PCIC_G2PIOGBASE_ECHG
#else
	    TX4927_PCIC_G2PIOGBASE_BSDIS
#endif
	    ;

	tx4927_pcicptr->g2piopbase = 0;

	tx4927_pcicptr->g2pmmask[0] = (mips_pci_mem_size - 1) >> 4;
	tx4927_pcicptr->g2pmgbase[0] = mips_pci_mem_base |
#ifdef __BIG_ENDIAN
	    TX4927_PCIC_G2PMnGBASE_ECHG
#else
	    TX4927_PCIC_G2PMnGBASE_BSDIS
#endif
	    ;
	tx4927_pcicptr->g2pmpbase[0] = mips_pci_mem_base;

	tx4927_pcicptr->g2pmmask[1] = 0;
	tx4927_pcicptr->g2pmgbase[1] = 0;
	tx4927_pcicptr->g2pmpbase[1] = 0;
	tx4927_pcicptr->g2pmmask[2] = 0;
	tx4927_pcicptr->g2pmgbase[2] = 0;
	tx4927_pcicptr->g2pmpbase[2] = 0;


	/* PCI->GB mappings (I/O 256B) */
	tx4927_pcicptr->p2giopbase = 0;	/* 256B */


#ifdef TX4927_SUPPORT_COMMAND_IO
	tx4927_pcicptr->p2giogbase = 0 | TX4927_PCIC_P2GIOGBASE_TIOEN |
#ifdef __BIG_ENDIAN
	    TX4927_PCIC_P2GIOGBASE_TECHG
#else
	    TX4927_PCIC_P2GIOGBASE_TBSDIS
#endif
	    ;
#else
	tx4927_pcicptr->p2giogbase = 0;
#endif

	/* PCI->GB mappings (MEM 512MB) M0 gets all of memory */
	tx4927_pcicptr->p2gm0plbase = 0;
	tx4927_pcicptr->p2gm0pubase = 0;
	tx4927_pcicptr->p2gmgbase[0] = 0 | TX4927_PCIC_P2GMnGBASE_TMEMEN |
#ifdef __BIG_ENDIAN
	    TX4927_PCIC_P2GMnGBASE_TECHG
#else
	    TX4927_PCIC_P2GMnGBASE_TBSDIS
#endif
	    ;