📄 m500auc.lst
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473 2 waitFor = 0x04;
474 2 break;
475 2 case PCD_LOADCONFIG: // IdleIRq cmd code: 0x07
476 2 case PCD_LOADKEYE2: // IdleIRq cmd code: 0x0b
477 2 case PCD_AUTHENT1: // IdleIRq cmd code: 0x0c
478 2 irqEn = 0x05;
479 2 waitFor = 0x04;
480 2 break;
481 2 case PCD_CALCCRC: // LoAlert and TxIRq cmd code: 0x12
482 2 irqEn = 0x11;
483 2 waitFor = 0x10;
484 2 break;
485 2 case PCD_AUTHENT2: // IdleIRq cmd code: 0x14
486 2 irqEn = 0x04;
487 2 waitFor = 0x04;
488 2 break;
C51 COMPILER V7.06 M500AUC 02/25/2005 08:31:58 PAGE 9
489 2 case PCD_RECEIVE: // HiAlert and IdleIRq cmd code: 0x16
490 2 info->nBitsReceived = -(ReadIO(RegBitFraming) >> 4);
491 2 irqEn = 0x06;
492 2 waitFor = 0x04;
493 2 break;
494 2 case PCD_LOADKEY: // IdleIRq cmd code: 0x19
495 2 irqEn = 0x05;
496 2 waitFor = 0x04;
497 2 break;
498 2 case PCD_TRANSMIT: // LoAlert and IdleIRq cmd code: 0x1a
499 2 irqEn = 0x05;
500 2 waitFor = 0x04;
501 2 break;
502 2 case PCD_TRANSCEIVE: // TxIrq, RxIrq, IdleIRq and LoAlert cmd code: 0x1e
503 2 info->nBitsReceived = -(ReadIO(RegBitFraming) >> 4);
504 2 irqEn = 0x3D;
505 2 waitFor = 0x04;
506 2 break;
507 2 default:
508 2 status = MI_UNKNOWN_COMMAND;
509 2 }
510 1 if (status == MI_OK)
511 1 {
512 2 // Initialize uC Timer for global Timeout management
513 2 irqEn |= 0x20; // always enable timout irq
514 2 waitFor |= 0x20; // always wait for timeout
515 2 Temp = ReadIO(RegInterruptEn);
516 2 start_timeout(4000); // initialise and start guard timer for reader
517 2 // 50us resolution, 200ms
518 2
519 2 WriteIO(RegInterruptEn,irqEn | 0x80); //necessary interrupts are enabled
520 2 WriteIO(RegCommand,cmd); //start command
521 2
522 2 // wait for commmand completion
523 2 // a command is completed, if the corresponding interrupt occurs
524 2 // or a timeout is signaled
525 2
526 2 while (!(MpIsrInfo->irqSource & waitFor
527 2 || T2IR)); // wait for cmd completion or timeout
528 2
529 2 WriteIO(RegInterruptEn,0x7F); // disable all interrupts
530 2 WriteIO(RegInterruptRq,0x7F); // clear all interrupt requests
531 2 SetBitMask(RegControl,0x04); // stop timer now
532 2
533 2 stop_timeout(); // stop timeout for reader
534 2 WriteIO(RegCommand,PCD_IDLE); // reset command register
535 2
536 2
537 2 if (!(MpIsrInfo->irqSource & waitFor)) // reader has not terminated
538 2 { // timer 2 expired
539 3 status = MI_ACCESSTIMEOUT;
540 3 }
541 2 else
542 2 status = MpIsrInfo->status; // set status
543 2
544 2 if (status == MI_OK) // no timeout error occured
545 2 {
546 3 if (tmpStatus = (ReadIO(RegErrorFlag) & 0x17)) // error occured
547 3 {
548 4 if (tmpStatus & 0x01) // collision detected
549 4 {
550 5 info->collPos = ReadIO(RegCollpos); // read collision position
C51 COMPILER V7.06 M500AUC 02/25/2005 08:31:58 PAGE 10
551 5 status = MI_COLLERR;
552 5 }
553 4 else
554 4 {
555 5 info->collPos = 0;
556 5 if (tmpStatus & 0x02) // parity error
557 5 {
558 6 status = MI_PARITYERR;
559 6 }
560 5 }
561 4 if (tmpStatus & 0x04) // framing error
562 4 {
563 5 status = MI_FRAMINGERR;
564 5 }
565 4 if (tmpStatus & 0x10) // FIFO overflow
566 4 {
567 5 FlushFIFO();
568 5 status = MI_OVFLERR;
569 5 }
570 4 if (tmpStatus & 0x08) //CRC error
571 4 {
572 5 status = MI_CRCERR;
573 5 }
574 4 if (status == MI_OK)
575 4 status = MI_NY_IMPLEMENTED;
576 4 // key error occures always, because of
577 4 // missing crypto 1 keys loaded
578 4 }
579 3 // if the last command was TRANSCEIVE, the number of
580 3 // received bits must be calculated - even if an error occured
581 3 if (cmd == PCD_TRANSCEIVE)
582 3 {
583 4 // number of bits in the last byte
584 4 lastBits = ReadIO(RegSecondaryStatus) & 0x07;
585 4 if (lastBits)
586 4 info->nBitsReceived += (info->nBytesReceived-1) * 8 + lastBits;
587 4 else
588 4 info->nBitsReceived += info->nBytesReceived * 8;
589 4 }
590 3 }
591 2 else
592 2 {
593 3 info->collPos = 0x00;
594 3 }
595 2 }
596 1 MpIsrInfo = 0; // reset interface variables for ISR
597 1 MpIsrOut = 0;
598 1 MpIsrIn = 0;
599 1 return status;
600 1 }
601
602 //////////////////////////////////////////////////////////////////////
603 // S E T A B I T M A S K
604 ///////////////////////////////////////////////////////////////////////
605 char SetBitMask(unsigned char reg,unsigned char mask) //
606 {
607 1 char data tmp = 0x0;
608 1
609 1 tmp = ReadIO(reg);
610 1 WriteIO(reg,tmp | mask); // set bit mask
611 1 return 0x0;
612 1 }
C51 COMPILER V7.06 M500AUC 02/25/2005 08:31:58 PAGE 11
613
614 //////////////////////////////////////////////////////////////////////
615 // C L E A R A B I T M A S K
616 ///////////////////////////////////////////////////////////////////////
617 char ClearBitMask(unsigned char reg,unsigned char mask) //
618 {
619 1 char data tmp = 0x0;
620 1
621 1 tmp = ReadIO(reg);
622 1 WriteIO(reg,tmp & ~mask); // clear bit mask
623 1 return 0x0;
624 1 }
625
626 ///////////////////////////////////////////////////////////////////////
627 // F L U S H F I F O
628 ///////////////////////////////////////////////////////////////////////
629 void FlushFIFO(void)
630 {
631 1 SetBitMask(RegControl,0x01);
632 1 }
633
634 ///////////////////////////////////////////////////////////////////////
635 // M I F A R E M O D U L E R E S E T
636 ///////////////////////////////////////////////////////////////////////
637 char M500PcdReset(void)
638 {
639 1 char data status = MI_OK;
640 1
641 1 RC500RST = FALSE; // clear reset pin
642 1 delay_1ms(25); // wait for 25ms
643 1 RC500RST = TRUE; // reset RC500
644 1 delay_50us(50); // wait for 2.5ms
645 1 RC500RST = FALSE; // clear reset pin
646 1
647 1 start_timeout(42000); // count down with a period of 50 us
648 1 // 42000 * 50 us = 2.1 s
649 1 // Temp = ReadRawIO(RegCommand);
650 1
651 1 // wait until reset command recognized
652 1 while (((ReadRawIO(RegCommand) & 0x3F) != 0x3F) && !T2IR);//读出复位命令码0x3f
653 1 // while reset sequence in progress
654 1 while ((ReadRawIO(RegCommand) & 0x3F) && !T2IR);//复位成功后读出数为0
655 1
656 1
657 1 stop_timeout(); // stop timeout counter
658 1
659 1 if (T2IR) // If reader timeout occurs
660 1 {
661 2 status = MI_RESETERR; // respose of reader IC is not correct
662 2 T2IR = 0;
663 2 }
664 1 else
665 1 {
666 2
667 2 // configure to linear address mode 配置成线性地址模式
668 2
669 2 WriteIO(0x00,0x00);
670 2 WriteIO(0x08,0x00);
671 2 WriteIO(0x10,0x00);
672 2 WriteIO(0x18,0x00);
673 2 WriteIO(0x20,0x00);
674 2 WriteIO(0x28,0x00);
C51 COMPILER V7.06 M500AUC 02/25/2005 08:31:58 PAGE 12
675 2 WriteIO(0x30,0x00);
676 2 WriteIO(0x38,0x00);
677 2
678 2 }
679 1 return status;
680 1 }
681
682 ///////////////////////////////////////////////////////////////////////
683 // M I F A R E M O D U L E C O N F I G U R A T I O N
684 ///////////////////////////////////////////////////////////////////////
685 char M500PcdConfig(void)
686 {
687 1 char data status;
688 1 char data i;
689 1 char data j;
690 1
691 1 if ((status = M500PcdReset()) == MI_OK)
692 1 {
693 2 delay_50us(100);
694 2
695 2 WriteIO(0x0,0x0);
696 2 // test clock Q calibration - value in the range of 0x46 expected
697 2 WriteIO(RegClockQControl,0x0);
698 2
699 2 Temp = ReadIO(RegClockQControl);
700 2
701 2 WriteIO(RegClockQControl,0x40);
702 2
703 2 Temp = ReadIO(RegClockQControl);
704 2
705 2 delay_50us(2); // wait approximately 100 us - calibration in progress
706 2 ClearBitMask(RegClockQControl,0x40); // clear bit ClkQCalib for
707 2 // further calibration
708 2
709 2 // The following values for RegBitPhase and
710 2 // RegRxThreshold represents an optimal
711 2 // value for our demo package. For user
712 2 // implementation some changes could be
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