📄 m500auc.lst
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234 // on the specified register. All bits with a 1 in the mask
235 // are cleared - all other bits keep their original value.
236 //
237 char ClearBitMask(unsigned char reg,unsigned char mask);
238
239 // _____________________________________________________________________________
240 //
241 // FUNCTION: FlushFIFO
C51 COMPILER V7.06 M500AUC 02/25/2005 08:31:58 PAGE 5
242 // IN: -
243 // OUT: -
244 // RETURN:
245 // COMMENT: All remaining date in the FIFO of the reader module is
246 // erased by this function. Before wrinting new data or
247 // starting a new command, all remaining data from former
248 // commands should be deleted. Please note, that in
249 // normal operation, never data should be left, that means
250 // that a call to this function should not be necessary.
251 //
252 void FlushFIFO(void);
253
254 // _____________________________________________________________________________
255 //
256 // FUNCTION: M500PiccAuthState
257 // IN: auth_mode
258 // snr
259 // sector
260 // OUT: -
261 // RETURN:
262 // COMMENT:
263 //
264 char M500PiccAuthState(unsigned char auth_mode,// PICC_AUTHENT1A, PICC_AUTHENT1B
265 unsigned char *snr, // 4 byte serial number
266 unsigned char sector); // 0 <= sector <= 15
267 // sector address for authentication
268
269 //////////////////////////////////////////////////////////////////////
270 // E X C H A N G E B Y T E S T R E A M
271 ///////////////////////////////////////////////////////////////////////
272 char ExchangeByteStream(unsigned char Cmd,
273 unsigned char *send_data,
274 unsigned char send_bytelen,
275 unsigned char *rec_data,
276 unsigned char *rec_bytelen);
277
278 ///////////////////////////////////////////////////////////////////////////////
279 // Handler RC500
280 // RC500 与Mifare 卡之间的数据通讯由中断服务程序完成
281 // 入口参数: 1. *MpIsrInfo 通讯参数结构指针
282 // 2. *MpIsrout 发送数据指针 send
283 // 3. *MpIsrin 接收数据指针 rec
284 ///////////////////////////////////////////////////////////////////////////////
285 void RC500ISR (void) interrupt 2 using 1 //Ext1 interrupt
286 {
287 1 static uchar data irqBits;
288 1 static uchar data irqMask;
289 1 static uchar data nbytes;
290 1 static uchar data cnt;
291 1
292 1 IE1 = 0; // Clear interrupt request flag
293 1
294 1 if (MpIsrInfo && MpIsrOut && MpIsrIn) // transfer pointers have to be set correctly
295 1 {
296 2 while( ReadRawIO(RegPrimaryStatus) & 0x08) // loop while IRQ pending
297 2 // Attention: IRQ bit is
298 2 // inverted when used with
299 2 // low activ IRQ
300 2 {
301 3 irqMask = ReadRawIO(RegInterruptEn); // read enabled interrupts
302 3 // read pending interrupts
303 3 irqBits = ReadRawIO(RegInterruptRq) & irqMask;//irqBits 表示何种中断
C51 COMPILER V7.06 M500AUC 02/25/2005 08:31:58 PAGE 6
304 3 MpIsrInfo->irqSource |= irqBits; // save pending interrupts
305 3 //************ LoAlertIRQ ******************
306 3 if (irqBits & 0x01) // LoAlert
307 3 {
308 4 // MFIFOLength = DEF_FIFO_LENGTH;
309 4
310 4 nbytes = MFIFOLength - ReadRawIO(RegFIFOLength);//计算FIFO 可以容纳的字节空间
311 4 // less bytes to send, than space in FIFO
312 4
313 4 if ((MpIsrInfo->nBytesToSend - MpIsrInfo->nBytesSent) <= nbytes)//需要发送的字节数<FIFO 可以容
-纳的字节空间 按照需要发送的字节数
314 4 {
315 5 nbytes = MpIsrInfo->nBytesToSend - MpIsrInfo->nBytesSent;//需要发送的字节数
316 5 WriteRawIO(RegInterruptEn,0x01); // disable LoAlert IRQ
317 5 }
318 4 // write remaining data to the FIFO
319 4 for ( cnt = 0;cnt < nbytes;cnt++)
320 4 {
321 5 WriteRawIO(RegFIFOData,MpIsrOut[MpIsrInfo->nBytesSent]);
322 5 MpIsrInfo->nBytesSent++;
323 5 }
324 4 WriteRawIO(RegInterruptRq,0x01); // reset IRQ bit
325 4 }
326 3
327 3 //************* TxIRQ Handling **************
328 3 if (irqBits & 0x10) // TxIRQ
329 3 {
330 4 WriteRawIO(RegInterruptRq,0x10); // reset IRQ bit
331 4 WriteRawIO(RegInterruptEn,0x82); // enable HiAlert Irq for
332 4 // response
333 4 if (MpIsrInfo->cmd == PICC_ANTICOLL1) // if cmd is anticollision
334 4 { // switch off parity generation
335 5 WriteRawIO(RegChannelRedundancy,0x02); // RXCRC and TXCRC disable, parity disable
336 5 }
337 4 }
338 3
339 3 //************* HiAlertIRQ or RxIRQ Handling ******************
340 3 if (irqBits & 0x0E) // HiAlert, Idle or RxIRQ
341 3 {
342 4 // read some bytes ( length of FIFO queue)
343 4 // into the receive buffer
344 4 nbytes = ReadRawIO(RegFIFOLength);
345 4 // read date from the FIFO and store them in the receive buffer
346 4 for ( cnt = 0; cnt < nbytes; cnt++)
347 4 {
348 5 MpIsrIn[MpIsrInfo->nBytesReceived] = ReadRawIO(RegFIFOData);
349 5 MpIsrInfo->nBytesReceived++;
350 5 Temp = MpIsrIn[MpIsrInfo->nBytesReceived] ;
351 5 }
352 4 WriteRawIO(RegInterruptRq,0x0A & irqBits);
353 4 // reset IRQ bit - idle irq will
354 4 // be deleted in a seperate section
355 4 }
356 3
357 3 //************** IdleIRQ Handling ***********
358 3 if (irqBits & 0x04) // Idle IRQ
359 3 {
360 4 WriteRawIO(RegInterruptEn,0x20); // disable Timer IRQ
361 4 WriteRawIO(RegInterruptRq,0x20); // disable Timer IRQ request
362 4 irqBits &= ~0x20; // clear Timer IRQ in local var
363 4 MpIsrInfo->irqSource &= ~0x20; // clear Timer IRQ in info var
364 4 // when idle received, then cancel
C51 COMPILER V7.06 M500AUC 02/25/2005 08:31:58 PAGE 7
365 4 // timeout
366 4 WriteRawIO(RegInterruptRq,0x04); // reset IRQ bit
367 4 // status should still be MI_OK
368 4 // no error - only used for wake up
369 4 }
370 3
371 3 //************* TimerIRQ Handling ***********
372 3 if (irqBits & 0x20) // timer IRQ
373 3 {
374 4 WriteRawIO(RegInterruptRq,0x20); // reset IRQ bit
375 4 MpIsrInfo->status = MI_NOTAGERR; // timeout error
376 4 // otherwise ignore the interrupt
377 4 }
378 3
379 3 }
380 2 }
381 1 }
382
383 ///////////////////////////////////////////////////////////////////////
384 // S e t T i m e o u t L E N G T H
385 ///////////////////////////////////////////////////////////////////////
386 void M500PcdSetTmo(unsigned char tmoLength)
387 {
388 1 switch(tmoLength)
389 1 { // timer clock frequency 13,56 MHz
390 2 case 1: // short timeout (1,0 ms)
391 2 WriteIO(RegTimerClock,0x07); // TAutoRestart=0,TPrescale=128
392 2 WriteIO(RegTimerReload,0x6a);// TReloadVal = 'h6a =106(dec)
393 2 break;
394 2 case 2: // medium timeout (1,5 ms)
395 2 WriteIO(RegTimerClock,0x07); // TAutoRestart=0,TPrescale=128
396 2 WriteIO(RegTimerReload,0xa0);// TReloadVal = 'ha0 =160(dec)
397 2 break;
398 2 case 3: // medium timeout (6 ms)
399 2 WriteIO(RegTimerClock,0x09); // TAutoRestart=0,TPrescale=4*128
400 2 WriteIO(RegTimerReload,0xa0);// TReloadVal = 'ha0 =160(dec)
401 2 break;
402 2 case 4: // long timeout (9.6 ms)
403 2 WriteIO(RegTimerClock,0x09); // TAutoRestart=0,TPrescale=4*128
404 2 WriteIO(RegTimerReload,0xff);// TReloadVal = 'hff =255(dec)
405 2 break;
406 2 case 5: // long timeout (38.5 ms)
407 2 WriteIO(RegTimerClock,0x0b); // TAutoRestart=0,TPrescale=16*128
408 2 WriteIO(RegTimerReload,0xff);// TReloadVal = 'hff =255(dec)
409 2 break;
410 2 case 6: // long timeout (154 ms)
411 2 WriteIO(RegTimerClock,0x0d); // TAutoRestart=0,TPrescale=64*128
412 2 WriteIO(RegTimerReload,0xff);// TReloadVal = 'hff =255(dec)
413 2 break;
414 2 case 7: // long timeout (616.2 ms)
415 2 WriteIO(RegTimerClock,0x0f); // TAutoRestart=0,TPrescale=256*128
416 2 WriteIO(RegTimerReload,0xff);// TReloadVal = 'hff =255(dec)
417 2 break;
418 2 default: //
419 2 WriteIO(RegTimerClock,0x07); // TAutoRestart=0,TPrescale=128
420 2 WriteIO(RegTimerReload,tmoLength);// TReloadVal = 'h6a =tmoLength(dec)
421 2 break;
422 2 }
423 1 }
424
425 //////////////////////////////////////////////////////////////////////
426 // W R I T E A P C D C O M M A N D
C51 COMPILER V7.06 M500AUC 02/25/2005 08:31:58 PAGE 8
427 ///////////////////////////////////////////////////////////////////////
428 char M500PcdCmd(unsigned char cmd,
429 volatile unsigned char* send,
430 volatile unsigned char* rcv,
431 volatile MfCmdInfo *info)
432 {
433 1 char data status = MI_OK;
434 1 char data tmpStatus ;
435 1 unsigned char data lastBits;
436 1
437 1 unsigned char data irqEn = 0x00;
438 1 unsigned char data waitFor = 0x00;
439 1 unsigned char data timerCtl = 0x00;
440 1 delay_50us(100);
441 1 WriteIO(0x0,0x0);
442 1 WriteIO(RegIRqPinConfig,0x03);
443 1
444 1 Temp = ReadIO(RegIRqPinConfig);
445 1 WriteIO(RegInterruptEn,0x7F); // disable all interrupts
446 1 Temp = ReadIO(RegInterruptEn);
447 1 WriteIO(RegInterruptRq,0x7F); // reset interrupt requests
448 1 Temp = ReadIO(RegInterruptRq);
449 1 WriteIO(RegCommand,PCD_IDLE); // terminate probably running command
450 1 Temp = ReadIO(RegCommand);
451 1 FlushFIFO(); // flush FIFO buffer
452 1
453 1 // save info structures to module pointers
454 1 MpIsrInfo = info;
455 1 MpIsrOut = send;
456 1 MpIsrIn = rcv;
457 1
458 1 info->irqSource = 0x0; // reset interrupt flags
459 1 // depending on the command code, appropriate interrupts are enabled (irqEn)
460 1 // and the commit interrupt is choosen (waitFor).
461 1 switch(cmd)
462 1 {
463 2 case PCD_IDLE: // nothing else required cmd code: 0x00
464 2 irqEn = 0x00;
465 2 waitFor = 0x00;
466 2 break;
467 2 case PCD_WRITEE2: // LoAlert and TxIRq cmd code: 0x01
468 2 irqEn = 0x11;
469 2 waitFor = 0x10;
470 2 break;
471 2 case PCD_READE2: // HiAlert, LoAlert and IdleIRq cmd code: 0x03
472 2 irqEn = 0x07;
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