📄 m500auc.lst
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459 1 MpIsrOut = send;
460 1 MpIsrIn = rcv;
461 1
462 1 info->irqSource = 0x0; // reset interrupt flags
463 1 // depending on the command code, appropriate interrupts are enabled (irqEn)
464 1 // and the commit interrupt is choosen (waitFor).
465 1 switch(cmd)
466 1 {
467 2 case PCD_IDLE: // nothing else required cmd code: 0x00
468 2 irqEn = 0x00;
469 2 waitFor = 0x00;
470 2 break;
471 2 case PCD_WRITEE2: // LoAlert and TxIRq cmd code: 0x01
472 2 irqEn = 0x11;
473 2 waitFor = 0x10;
474 2 break;
475 2 case PCD_READE2: // HiAlert, LoAlert and IdleIRq cmd code: 0x03
476 2 irqEn = 0x07;
477 2 waitFor = 0x04;
478 2 break;
479 2 case PCD_LOADCONFIG: // IdleIRq cmd code: 0x07
480 2 case PCD_LOADKEYE2: // IdleIRq cmd code: 0x0b
481 2
482 2 case PCD_AUTHENT1: // IdleIRq cmd code: 0x0c
483 2 irqEn = 0x05;
484 2 waitFor = 0x04;
485 2 break;
486 2 case PCD_CALCCRC: // LoAlert and TxIRq cmd code: 0x12
487 2 irqEn = 0x11;
488 2 waitFor = 0x10;
C51 COMPILER V7.06 M500AUC 03/21/2005 16:36:23 PAGE 9
489 2 break;
490 2 case PCD_AUTHENT2: // IdleIRq cmd code: 0x14
491 2 irqEn = 0x04;
492 2 waitFor = 0x04;
493 2 break;
494 2 case PCD_RECEIVE: // HiAlert and IdleIRq cmd code: 0x16
495 2 info->nBitsReceived = -(ReadIO(RegBitFraming) >> 4);
496 2 irqEn = 0x06;
497 2 waitFor = 0x04;
498 2 break;
499 2 case PCD_LOADKEY: // IdleIRq cmd code: 0x19
500 2 irqEn = 0x05;
501 2 waitFor = 0x04;
502 2 break;
503 2 case PCD_TRANSMIT: // LoAlert and IdleIRq cmd code: 0x1a
504 2 irqEn = 0x05;
505 2 waitFor = 0x04;
506 2 break;
507 2 case PCD_TRANSCEIVE: // TxIrq, RxIrq, IdleIRq and LoAlert cmd code: 0x1e
508 2 info->nBitsReceived = -(ReadIO(RegBitFraming) >> 4);
509 2 irqEn = 0x3D;
510 2 waitFor = 0x04;
511 2 break;
512 2 default:
513 2 status = MI_UNKNOWN_COMMAND;
514 2 }
515 1 if (status == MI_OK)
516 1 {
517 2 // Initialize uC Timer for global Timeout management
518 2 irqEn |= 0x20; // always enable timout irq
519 2 waitFor |= 0x20; // always wait for timeout
520 2 Temp = ReadIO(RegInterruptEn);
521 2 start_timeout(4000); // initialise and start guard timer for reader
522 2 // 50us resolution, 200ms
523 2
524 2 WriteIO(RegInterruptEn,irqEn | 0x80); //necessary interrupts are enabled
525 2 WriteIO(RegCommand,cmd); //start command
526 2
527 2 // wait for commmand completion
528 2 // a command is completed, if the corresponding interrupt occurs
529 2 // or a timeout is signaled
530 2
531 2 while (!(MpIsrInfo->irqSource & waitFor
532 2 || T2IR)); // wait for cmd completion or timeout
533 2
534 2 WriteIO(RegInterruptEn,0x7F); // disable all interrupts
535 2 WriteIO(RegInterruptRq,0x7F); // clear all interrupt requests
536 2 SetBitMask(RegControl,0x04); // stop timer now
537 2
538 2 stop_timeout(); // stop timeout for reader
539 2 WriteIO(RegCommand,PCD_IDLE); // reset command register
540 2
541 2
542 2 if (!(MpIsrInfo->irqSource & waitFor)) // reader has not terminated
543 2 { // timer 2 expired
544 3 status = MI_ACCESSTIMEOUT;
545 3 }
546 2 else
547 2 status = MpIsrInfo->status; // set status
548 2
549 2 if (status == MI_OK) // no timeout error occured
550 2 {
C51 COMPILER V7.06 M500AUC 03/21/2005 16:36:23 PAGE 10
551 3 if (tmpStatus = (ReadIO(RegErrorFlag) & 0x17)) // error occured
552 3 {
553 4 if (tmpStatus & 0x01) // collision detected
554 4 {
555 5 info->collPos = ReadIO(RegCollpos); // read collision position
556 5 status = MI_COLLERR;
557 5 }
558 4 else
559 4 {
560 5 info->collPos = 0;
561 5 if (tmpStatus & 0x02) // parity error
562 5 {
563 6 status = MI_PARITYERR;
564 6 }
565 5 }
566 4 if (tmpStatus & 0x04) // framing error
567 4 {
568 5 status = MI_FRAMINGERR;
569 5 }
570 4 if (tmpStatus & 0x10) // FIFO overflow
571 4 {
572 5 FlushFIFO();
573 5 status = MI_OVFLERR;
574 5 }
575 4 if (tmpStatus & 0x08) //CRC error
576 4 {
577 5 status = MI_CRCERR;
578 5 }
579 4 if (status == MI_OK)
580 4 status = MI_NY_IMPLEMENTED;
581 4 // key error occures always, because of
582 4 // missing crypto 1 keys loaded
583 4 }
584 3 // if the last command was TRANSCEIVE, the number of
585 3 // received bits must be calculated - even if an error occured
586 3 if (cmd == PCD_TRANSCEIVE)
587 3 {
588 4 // number of bits in the last byte
589 4 lastBits = ReadIO(RegSecondaryStatus) & 0x07;
590 4 if (lastBits)
591 4 info->nBitsReceived += (info->nBytesReceived-1) * 8 + lastBits;
592 4 else
593 4 info->nBitsReceived += info->nBytesReceived * 8;
594 4 }
595 3 }
596 2 else
597 2 {
598 3 info->collPos = 0x00;
599 3 }
600 2 }
601 1 MpIsrInfo = 0; // reset interface variables for ISR
602 1 MpIsrOut = 0;
603 1 MpIsrIn = 0;
604 1 return status;
605 1 }
606
607 //////////////////////////////////////////////////////////////////////
608 // S E T A B I T M A S K（屏蔽）设置一屏蔽位
609 ///////////////////////////////////////////////////////////////////////
610 char SetBitMask(unsigned char reg,unsigned char mask) //
611 {
612 1 char data tmp = 0x0;
C51 COMPILER V7.06 M500AUC 03/21/2005 16:36:23 PAGE 11
613 1
614 1 tmp = ReadIO(reg);
615 1 WriteIO(reg,tmp | mask); // set bit mask
616 1 return 0x0;
617 1 }
618
619 //////////////////////////////////////////////////////////////////////
620 // C L E A R A B I T M A S K（清除一屏蔽位）
621 ///////////////////////////////////////////////////////////////////////
622 char ClearBitMask(unsigned char reg,unsigned char mask) //
623 {
624 1 char data tmp = 0x0;
625 1
626 1 tmp = ReadIO(reg);
627 1 WriteIO(reg,tmp & ~mask); // clear bit mask
628 1 return 0x0;
629 1 }
630
631 ///////////////////////////////////////////////////////////////////////
632 // F L U S H F I F O（清除FIFO的内容)
633 ///////////////////////////////////////////////////////////////////////
634 void FlushFIFO(void)
635 {
636 1 SetBitMask(RegControl,0x01);
637 1 }
638
639 ///////////////////////////////////////////////////////////////////////
640 // M I F A R E M O D U L E R E S E T
641 ///////////////////////////////////////////////////////////////////////
642 char M500PcdReset(void)
643 {
644 1 char data status = MI_OK;
645 1
646 1 RC500RST = FALSE; // clear reset pin
647 1 delay_1ms(25); // wait for 25ms
648 1 RC500RST = TRUE; // reset RC500
649 1 delay_50us(50); // wait for 2.5ms
650 1 RC500RST = FALSE; // clear reset pin
651 1
652 1 start_timeout(42000); // count down with a period of 50 us
653 1 // 42000 * 50 us = 2.1 s
654 1 // Temp = ReadRawIO(RegCommand);
655 1
656 1 // wait until reset command recognized
657 1 while (((ReadRawIO(RegCommand) & 0x3F) != 0x3F) && !T2IR);//读出复位命令码0x3f
658 1 // while reset sequence in progress
659 1 while ((ReadRawIO(RegCommand) & 0x3F) && !T2IR);//复位成功后读出数为0
660 1
661 1
662 1 stop_timeout(); // stop timeout counter
663 1
664 1 if (T2IR) // If reader timeout occurs
665 1 {
666 2 status = MI_RESETERR; // respose of reader IC is not correct
667 2 T2IR = 0;
668 2 }
669 1 else
670 1 {
671 2
672 2 // configure to linear address mode 配置成线性地址模式
673 2 // 用6比bit直接地址访问
674 2
C51 COMPILER V7.06 M500AUC 03/21/2005 16:36:23 PAGE 12
675 2 WriteIO(0x00,0x00);
676 2 WriteIO(0x08,0x00);
677 2 WriteIO(0x10,0x00);
678 2 WriteIO(0x18,0x00);
679 2 WriteIO(0x20,0x00);
680 2 WriteIO(0x28,0x00);
681 2 WriteIO(0x30,0x00);
682 2 WriteIO(0x38,0x00);
683 2
684 2 }
685 1 return status;
686 1 }
687
688 ///////////////////////////////////////////////////////////////////////
689 // M I F A R E M O D U L E C O N F I G U R A T I O N
690 ///////////////////////////////////////////////////////////////////////
691 char M500PcdConfig(void)
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