boot.s

关于软中断和semihosting的一个程序,根据ADS1.2源代码修改,希望能对大家有帮助

;----------------------------------------------------------------------
; Area Definition 
;----------------------------------------------------------------------

 
            AREA boot, CODE, READONLY 
			EXPORT  swi_handler
			IMPORT  C_SWI_Handler

			INCLUDE s3c2410.s
T_bit   equ   0x20
;----------------------------------------------------------------------
; Define the entry point

;obey E:\swi_test\swi\ads_ul_cfg.txt
; ---------------------------------------------------------------------
	EXPORT __ENTRY	
__ENTRY

    bl     reset_handler
    bl     undefined_handler
    bl     swi_handler
    bl     prefetch_handler
    bl     abort_handler
    nop     ; reserve vector
    bl     irq_handler
    bl     fiq_handler
       


    	MACRO
$HandlerLabel HANDLER $HandleLabel

$HandlerLabel
	sub	    sp,sp,#4        ;decrement sp(to store jump address)
	stmfd	sp!,{r0}        ;PUSH the work register to stack(lr does't push because it return to original address)
	ldr     r0,=$HandleLabel;load the address of HandleXXX to r0
	ldr     r0,[r0]         ;load the contents(service routine start address) of HandleXXX
	str     r0,[sp,#4]      ;store the contents(ISR) of HandleXXX to stack
	ldmfd   sp!,{r0,pc}     ;POP the work register and pc(jump to ISR)
	MEND

fiq_handler        HANDLER HandleFIQ
irq_handler        HANDLER HandleIRQ
undefined_handler  HANDLER HandleUndef
;swi_handler        HANDLER HandleSWI
prefetch_handler   HANDLER HandlePabort
abort_handler      HANDLER HandleDabort

IsrIRQ  
	sub	sp, sp, #4       ;reserved for PC
	stmfd	sp!, {r8-r9}
	
	ldr	r9, =INTOFFSET
	ldr	r9, [r9]
	ldr	r8, =HandleEINT0
	add	r8, r8,r9,lsl #2
	ldr	r8, [r8]
	str	r8, [sp,#8]
	ldmfd	sp!,{r8-r9,pc}

;---------------------------
; the actual reset code
;----------------------------
reset_handler

   ; set the cpu to SVC32 mode
;    mrs     r0, cpsr
;    bic     r0, r0, #0x1f
;    orr     r0, r0, #0xd3
;    msr     cpsr_cxsf, r0
    
   ; set the cpu to USR32 mode
    mrs     r0, cpsr
    bic     r0, r0, #0x1f
    orr     r0, r0, #0xd0
    msr     cpsr_cxsf, r0
   
   ; watch dog disable 
    ldr     r0, =WTCON       
    ldr     r1, =0x0         
    str     r1, [r0]
   
   ; all interrupt disable
    ldr     r0, =INTMSK
    ldr     r1, =0xffffffff  
    str     r1, [r0]

   ; all sub interrupt disable
    ldr     r0, =INTSUBMSK
    ldr     r1, =0x3ff
    str     r1, [r0]

  	; Setup IRQ handler
	ldr	r0,=HandleIRQ       ;This routine is needed
	ldr	r1,=IsrIRQ          ;if there isn't 'subs pc,lr,#4' at 0x18, 0x1c
	str	r1,[r0]

   ;// FCLK:HCLK:PCLK = 1:2:4 
   ;// default FCLK is 120 MHz ! 
   ;// ldr     r0, =CLKDIVN
   ;// mov     r1, #3
   ;// str     r1, [r0]

	ldr	r0,=0x56000070
	ldr	r1,=0x280000
    str	r1,[r0]

   ; Set memory control registers
    ldr     r0, =InitTableEBI
    ldr     r1, =BWSCON         ; BWSCON Address
    add     r2, r0, #52         ; total 13 memory contrl registers 
0       
    ldr     r3, [r0], #4    
    str     r3, [r1], #4    
    cmp     r2, r0
    bne     %B0

    

;-------------------------------------
; Initialize STACK pointer
;-------------------------------------
    mrs    r0, cpsr
    bic    r0, r0, #LOCKOUT | MODE_MASK
    orr    r2, r0, #USR_MODE

; Set up Fast Interrupt Mode and set FIQ Mode Stack
    orr    r1, r0, #LOCKOUT | FIQ_MODE
    msr    cpsr_cxsf, r1
    msr    spsr_cxsf, r2 
    ldr    sp, =FIQ_STACK

; Set up Interrupt Mode and set IRQ Mode Stack
    orr    r1, r0, #LOCKOUT | IRQ_MODE
    msr    cpsr_cxsf, r1
    msr    spsr_cxsf, r2		  
    ldr    sp, =IRQ_STACK

; Set up Abort Mode and set Abort Mode Stack
    orr    r1, r0, #LOCKOUT | ABT_MODE
    msr    cpsr_cxsf, r1
    msr    spsr_cxsf, r2
    ldr    sp, =ABT_STACK 

; Set up Undefined Instruction Mode and set Undef Mode Stack
    orr    r1, r0, #LOCKOUT | UDF_MODE
    msr    cpsr_cxsf, r1
    msr    spsr_cxsf, r2 
    ldr    sp, =UDF_STACK
 
; Set up Supervisor Mode and set Supervisor Mode Stack
    orr    r1, r0, #SUP_MODE 
    msr    cpsr_cxsf, r1
    msr    spsr_cxsf, r2 
    ldr    sp, =SUP_STACK ; Change CPSR to SVC mode

;-----------------------
; Jump to C code
;-----------------------
;   IMPORT Main
;    b   Main
    
    IMPORT __main
	 b      __main
    

;       IMPORT   |Image$$RO$$Base|                
;       IMPORT   |Image$$RO$$Limit|
;       IMPORT   |Image$$RW$$Limit|
;       IMPORT   |Image$$ZI$$Base|
;       IMPORT   |Image$$ZI$$Limit|

;PtTextStart        DCD     |Image$$RO$$Base|
;;PtDataEnd          DCD     |Image$$RW$$Limit|
;PtBssStart         DCD     |Image$$ZI$$Base|
;PtBssEnd           DCD     |Image$$ZI$$Limit|

;-------------------------
; The location of stacks
;-------------------------
USER_STACK         EQU     (STACK_BASEADDRESS-0x3800)   ;0x33ff4800  
SUP_STACK          EQU     (STACK_BASEADDRESS-0x2800)   ;0x33ff5800 
UDF_STACK          EQU     (STACK_BASEADDRESS-0x2400)   ;0x33ff5c00 
ABT_STACK          EQU     (STACK_BASEADDRESS-0x2000)   ;0x33ff6000 
IRQ_STACK          EQU     (STACK_BASEADDRESS-0x1000)   ;0x33ff7000 
FIQ_STACK          EQU     (STACK_BASEADDRESS-0x0)      ;0x33ff8000  

InitTableEBI
;Modified by Zhomh
   DCD     0x62669214      ; BWSCON
   DCD     0x00000700      ; BANKCON0
   DCD     0x00007FFC      ; BANKCON1
;   DCD     0x00000700      ; BANKCON2 
   DCD     0x00000700      ; BANKCON2
   DCD     0x00007ffc      ; BANKCON3 
   DCD     0x00000700      ; BANKCON4 
   DCD     0x00000700      ; BANKCON5 
   DCD     0x00018005      ; BANKCON6 
   DCD     0x00000700      ; BANKCON7 
   DCD     0x008E0459      ; REFRESH
   DCD     0x00000022      ; BANKSIZE
   DCD     0x00000030      ; MRSRB6
   DCD     0x00000030      ; MRSRB7




swi_handler

    STMFD   sp!, {r0-r3, r12, lr}  ; Store registers
    MOV     r1, sp                 ; Set pointer to parameters
    MRS     r0, spsr               ; Get spsr
    STMFD   sp!, {r0}              ; Store spsr onto stack
    TST     r0, #T_bit             ; Occurred in Thumb state?
    LDRNEH  r0, [lr,#-2]           ; Yes: Load halfword and...
    BICNE   r0, r0, #0xFF00        ; ...extract comment field
    LDREQ   r0, [lr,#-4]           ; No: Load word and...
    BICEQ   r0, r0, #0xFF000000    ; ...extract comment field

        ; r0 now contains SWI number
        ; r1 now contains pointer to stacked registers

    BL      C_SWI_Handler          ; Call main part of handler
    LDMFD   sp!, {r0}              ; Get spsr from stack
    MSR     spsr_cf, r0            ; Restore spsr
    LDMFD   sp!, {r0-r3, r12, pc}^ ; Restore registers and return

 


    ALIGN


    AREA RamData, DATA, READWRITE

        ^   ISR_STARTADDRESS
HandleReset    #   4
HandleUndef    #   4
HandleSWI      #   4
HandlePabort   #   4
HandleDabort   #   4
HandleReserved #   4
HandleIRQ      #   4
HandleFIQ      #   4

;Don't use the label 'IntVectorTable',
;The value of IntVectorTable is different with the address you think it 
;IntVectorTable
HandleEINT0    #   4
HandleEINT1    #   4
HandleEINT2    #   4
HandleEINT3    #   4
HandleEINT4_7  #   4
HandleEINT8_23 #   4
HandleRSV6     #   4
HandleBATFLT   #   4
HandleTICK     #   4
HandleWDT      #   4
HandleTIMER0   #   4
HandleTIMER1   #   4
HandleTIMER2   #   4
HandleTIMER3   #   4
HandleTIMER4   #   4
HandleUART2    #   4
HandleLCD      #   4
HandleDMA0     #   4
HandleDMA1     #   4
HandleDMA2     #   4
HandleDMA3     #   4
HandleMMC      #   4
HandleSPI0     #   4
HandleUART1    #   4
HandleRSV24    #   4
HandleUSBD     #   4
HandleUSBH     #   4
HandleIIC      #   4
HandleUART0    #   4
HandleSPI1     #   4
HandleRTC      #   4
HandleADC      #   4

        END