s3c2410.s

关于软中断和semihosting的一个程序,根据ADS1.2源代码修改,希望能对大家有帮助

;------------------------------------------------------------------------------
;                                                                     
; File Name        :  s3c2410.s                
; Board Version    :  ST2410_V2.0 uDragon technology Corp.
; Describe         :  define ARM register and S3C2410 register value
; Author           :  shen cheng                                                                
; Date             :  2005-7-8
;      
;------------------------------------------------------------------------------

STACK_BASEADDRESS	EQU 0x33ff8000  
ISR_STARTADDRESS	EQU 0x33ffff00

;---------------------------------------------------------------------------
; Format of the Program Status Register                                 
;---------------------------------------------------------------------------
;                                                                       
;     31  30  29   28         7   6   5   4   3   2   1   0                  
;    +---+---+---+---+--ss--+---+---+---+---+---+---+---+---+               
;    | N | Z | C | V |      | I | F | T |     M4 ~ M0       |               
;    +---+---+---+---+--ss--+---+---+---+---+---+---+---+---+               
; 
;---------------------------------------------------------------------------
; Processor Mode and Mask                                                  
;---------------------------------------------------------------------------

FBit		    EQU	    &40
IBit		    EQU	    &80
LOCKOUT         EQU     &C0       ;Interrupt lockout value
LOCK_MSK        EQU     &C0       ;Interrupt lockout mask value
MODE_MASK       EQU     &1F       ;Processor Mode Mask
UDF_MODE        EQU     &1B       ;Undefine Mode(UDF)
ABT_MODE        EQU     &17       ;Abort Mode(ABT)
SUP_MODE        EQU     &13       ;Supervisor Mode (SVC)
IRQ_MODE        EQU     &12       ;Interrupt Mode (IRQ)
FIQ_MODE        EQU     &11       ;Fast Interrupt Mode (FIQ)
USR_MODE        EQU     &10       ;User Mode(USR)

;=================
; Memory control 
;=================
BWSCON      EQU  0x48000000     ;Bus width & wait status
BANKCON0    EQU  0x48000004     ;Boot ROM control
BANKCON1    EQU  0x48000008     ;BANK1 control
BANKCON2    EQU  0x4800000c     ;BANK2 cControl
BANKCON3    EQU  0x48000010     ;BANK3 control
BANKCON4    EQU  0x48000014     ;BANK4 control
BANKCON5    EQU  0x48000018     ;BANK5 control
BANKCON6    EQU  0x4800001c     ;BANK6 control
BANKCON7    EQU  0x48000020     ;BANK7 control
REFRESH     EQU  0x48000024     ;DRAM/SDRAM refresh
BANKSIZE    EQU  0x48000028     ;Flexible Bank Size
MRSRB6      EQU  0x4800002c     ;Mode register set for SDRAM
MRSRB7      EQU  0x48000030     ;Mode register set for SDRAM

;=================
; INTERRUPT
;=================
SRCPND       EQU  0x4a000000    ;Interrupt request status
INTMOD       EQU  0x4a000004    ;Interrupt mode control
INTMSK       EQU  0x4a000008    ;Interrupt mask control
PRIORITY     EQU  0x4a00000a    ;IRQ priority control
INTPND       EQU  0x4a000010    ;Interrupt request status
INTOFFSET    EQU  0x4a000014    ;Interruot request source offset
SUSSRCPND    EQU  0x4a000018    ;Sub source pending
INTSUBMSK    EQU  0x4a00001c    ;Interrupt sub mask

;==========================
; CLOCK & POWER MANAGEMENT
;==========================
LOCKTIME    EQU  0x4c000000     ;PLL lock time counter
MPLLCON     EQU  0x4c000004     ;MPLL Control
UPLLCON     EQU  0x4c000008     ;UPLL Control
CLKCON      EQU  0x4c00000c     ;Clock generator control
CLKSLOW     EQU  0x4c000010     ;Slow clock control
CLKDIVN     EQU  0x4c000014     ;Clock divider control


;=================
; WATCH DOG TIMER
;=================
WTCON     EQU  0x53000000       ;Watch-dog timer mode
WTDAT     EQU  0x53000004       ;Watch-dog timer data
WTCNT     EQU  0x53000008       ;Eatch-dog timer count

    END