etherdp83820.c

这是一个同样来自贝尔实验室的和UNIX有着渊源的操作系统, 其简洁的设计和实现易于我们学习和理解

/*
 * National Semiconductor DP83820 & DP83821
 * 10/100/1000 Mb/s Ethernet Network Interface Controller
 * (Gig-NIC).
 * Driver assumes little-endian and 32-bit host throughout.
 */
#ifdef FS
#include "all.h"
#include "io.h"
#include "mem.h"
#include "../ip/ip.h"

#else

#include "u.h"
#include "../port/lib.h"
#include "mem.h"
#include "dat.h"
#include "fns.h"
#include "io.h"
#include "../port/error.h"
#include "../port/netif.h"
#endif			/* FS */

#include "etherif.h"
#include "ethermii.h"

#include "compat.h"

enum {					/* Registers */
	Cr		= 0x00,		/* Command */
	Cfg		= 0x04,		/* Configuration and Media Status */
	Mear		= 0x08,		/* MII/EEPROM Access */
	Ptscr		= 0x0C,		/* PCI Test Control */
	Isr		= 0x10,		/* Interrupt Status */
	Imr		= 0x14,		/* Interrupt Mask */
	Ier		= 0x18,		/* Interrupt Enable */
	Ihr		= 0x1C,		/* Interrupt Holdoff */
	Txdp		= 0x20,		/* Transmit Descriptor Pointer */
	Txdphi		= 0x24,		/* Transmit Descriptor Pointer Hi */
	Txcfg		= 0x28,		/* Transmit Configuration */
	Gpior		= 0x2C,		/* General Purpose I/O Control */
	Rxdp		= 0x30,		/* Receive Descriptor Pointer */
	Rxdphi		= 0x34,		/* Receive Descriptor Pointer Hi */
	Rxcfg		= 0x38,		/* Receive Configuration */
	Pqcr		= 0x3C,		/* Priority Queueing Control */
	Wcsr		= 0x40,		/* Wake on LAN Control/Status */
	Pcr		= 0x44,		/* Pause Control/Status */
	Rfcr		= 0x48,		/* Receive Filter/Match Control */
	Rfdr		= 0x4C,		/* Receive Filter/Match Data */
	Brar		= 0x50,		/* Boot ROM Address */
	Brdr		= 0x54,		/* Boot ROM Data */
	Srr		= 0x58,		/* Silicon Revision */
	Mibc		= 0x5C,		/* MIB Control */
	Mibd		= 0x60,		/* MIB Data */
	Txdp1		= 0xA0,		/* Txdp Priority 1 */
	Txdp2		= 0xA4,		/* Txdp Priority 2 */
	Txdp3		= 0xA8,		/* Txdp Priority 3 */
	Rxdp1		= 0xB0,		/* Rxdp Priority 1 */
	Rxdp2		= 0xB4,		/* Rxdp Priority 2 */
	Rxdp3		= 0xB8,		/* Rxdp Priority 3 */
	Vrcr		= 0xBC,		/* VLAN/IP Receive Control */
	Vtcr		= 0xC0,		/* VLAN/IP Transmit Control */
	Vdr		= 0xC4,		/* VLAN Data */
	Ccsr		= 0xCC,		/* Clockrun Control/Status */
	Tbicr		= 0xE0,		/* TBI Control */
	Tbisr		= 0xE4,		/* TBI Status */
	Tanar		= 0xE8,		/* TBI ANAR */
	Tanlpar		= 0xEC,		/* TBI ANLPAR */
	Taner		= 0xF0,		/* TBI ANER */
	Tesr		= 0xF4,		/* TBI ESR */
};

enum {					/* Cr */
	Txe		= 0x00000001,	/* Transmit Enable */
	Txd		= 0x00000002,	/* Transmit Disable */
	Rxe		= 0x00000004,	/* Receiver Enable */
	Rxd		= 0x00000008,	/* Receiver Disable */
	Txr		= 0x00000010,	/* Transmitter Reset */
	Rxr		= 0x00000020,	/* Receiver Reset */
	Swien		= 0x00000080,	/* Software Interrupt Enable */
	Rst		= 0x00000100,	/* Reset */
	TxpriSHFT	= 9,		/* Tx Priority Queue Select */
	TxpriMASK	= 0x00001E00,
	RxpriSHFT	= 13,		/* Rx Priority Queue Select */
	RxpriMASK	= 0x0001E000,
};

enum {					/* Configuration and Media Status */
	Bem		= 0x00000001,	/* Big Endian Mode */
	Ext125		= 0x00000002,	/* External 125MHz reference Select */
	Bromdis		= 0x00000004,	/* Disable Boot ROM interface */
	Pesel		= 0x00000008,	/* Parity Error Detection Action */
	Exd		= 0x00000010,	/* Excessive Deferral Abort */
	Pow		= 0x00000020,	/* Program Out of Window Timer */
	Sb		= 0x00000040,	/* Single Back-off */
	Reqalg		= 0x00000080,	/* PCI Bus Request Algorithm */
	Extstsen	= 0x00000100,	/* Extended Status Enable */
	Phydis		= 0x00000200,	/* Disable PHY */
	Phyrst		= 0x00000400,	/* Reset PHY */
	M64addren	= 0x00000800,	/* Master 64-bit Addressing Enable */
	Data64en	= 0x00001000,	/* 64-bit Data Enable */
	Pci64det	= 0x00002000,	/* PCI 64-bit Bus Detected */
	T64addren	= 0x00004000,	/* Target 64-bit Addressing Enable */
	Mwidis		= 0x00008000,	/* MWI Disable */
	Mrmdis		= 0x00010000,	/* MRM Disable */
	Tmrtest		= 0x00020000,	/* Timer Test Mode */
	Spdstsien	= 0x00040000,	/* PHY Spdsts Interrupt Enable */
	Lnkstsien	= 0x00080000,	/* PHY Lnksts Interrupt Enable */
	Dupstsien	= 0x00100000,	/* PHY Dupsts Interrupt Enable */
	Mode1000	= 0x00400000,	/* 1000Mb/s Mode Control */
	Tbien		= 0x01000000,	/* Ten-Bit Interface Enable */
	Dupsts		= 0x10000000,	/* Full Duplex Status */
	Spdsts100	= 0x20000000,	/* SPEED100 Input Pin Status */
	Spdsts1000	= 0x40000000,	/* SPEED1000 Input Pin Status */
	Lnksts		= 0x80000000,	/* Link Status */
};

enum {					/* MII/EEPROM Access */
	Eedi		= 0x00000001,	/* EEPROM Data In */
	Eedo		= 0x00000002,	/* EEPROM Data Out */
	Eeclk		= 0x00000004,	/* EEPROM Serial Clock */
	Eesel		= 0x00000008,	/* EEPROM Chip Select */
	Mdio		= 0x00000010,	/* MII Management Data */
	Mddir		= 0x00000020,	/* MII Management Direction */
	Mdc		= 0x00000040,	/* MII Management Clock */
};

enum {					/* Interrupts */
	Rxok		= 0x00000001,	/* Rx OK */
	Rxdesc		= 0x00000002,	/* Rx Descriptor */
	Rxerr		= 0x00000004,	/* Rx Packet Error */
	Rxearly		= 0x00000008,	/* Rx Early Threshold */
	Rxidle		= 0x00000010,	/* Rx Idle */
	Rxorn		= 0x00000020,	/* Rx Overrun */
	Txok		= 0x00000040,	/* Tx Packet OK */
	Txdesc		= 0x00000080,	/* Tx Descriptor */
	Txerr		= 0x00000100,	/* Tx Packet Error */
	Txidle		= 0x00000200,	/* Tx Idle */
	Txurn		= 0x00000400,	/* Tx Underrun */
	Mib		= 0x00000800,	/* MIB Service */
	Swi		= 0x00001000,	/* Software Interrupt */
	Pme		= 0x00002000,	/* Power Management Event */
	Phy		= 0x00004000,	/* PHY Interrupt */
	Hibint		= 0x00008000,	/* High Bits Interrupt Set */
	Rxsovr		= 0x00010000,	/* Rx Status FIFO Overrun */
	Rtabt		= 0x00020000,	/* Received Target Abort */
	Rmabt		= 0x00040000,	/* Received Master Abort */
	Sserr		= 0x00080000,	/* Signalled System Error */
	Dperr		= 0x00100000,	/* Detected Parity Error */
	Rxrcmp		= 0x00200000,	/* Receive Reset Complete */
	Txrcmp		= 0x00400000,	/* Transmit Reset Complete */
	Rxdesc0		= 0x00800000,	/* Rx Descriptor for Priority Queue 0 */
	Rxdesc1		= 0x01000000,	/* Rx Descriptor for Priority Queue 1 */
	Rxdesc2		= 0x02000000,	/* Rx Descriptor for Priority Queue 2 */
	Rxdesc3		= 0x04000000,	/* Rx Descriptor for Priority Queue 3 */
	Txdesc0		= 0x08000000,	/* Tx Descriptor for Priority Queue 0 */
	Txdesc1		= 0x10000000,	/* Tx Descriptor for Priority Queue 1 */
	Txdesc2		= 0x20000000,	/* Tx Descriptor for Priority Queue 2 */
	Txdesc3		= 0x40000000,	/* Tx Descriptor for Priority Queue 3 */
};

enum {					/* Interrupt Enable */
	Ien		= 0x00000001,	/* Interrupt Enable */
};

enum {					/* Interrupt Holdoff */
	IhSHFT		= 0,		/* Interrupt Holdoff */
	IhMASK		= 0x000000FF,
	Ihctl		= 0x00000100,	/* Interrupt Holdoff Control */
};

enum {					/* Transmit Configuration */
	TxdrthSHFT	= 0,		/* Tx Drain Threshold */
	TxdrthMASK	= 0x000000FF,
	FlthSHFT	= 16,		/* Tx Fill Threshold */
	FlthMASK	= 0x0000FF00,
	Brstdis		= 0x00080000,	/* 1000Mb/s Burst Disable */
	MxdmaSHFT	= 20,		/* Max Size per Tx DMA Burst */
	MxdmaMASK	= 0x00700000,
	Ecretryen	= 0x00800000,	/* Excessive Collision Retry Enable */
	Atp		= 0x10000000,	/* Automatic Transmit Padding */
	Mlb		= 0x20000000,	/* MAC Loopback */
	Hbi		= 0x40000000,	/* Heartbeat Ignore */
	Csi		= 0x80000000,	/* Carrier Sense Ignore */
};

enum {					/* Receive Configuration */
	RxdrthSHFT	= 1,		/* Rx Drain Threshold */
	RxdrthMASK	= 0x0000003E,
	Airl		= 0x04000000,	/* Accept In-Range Length Errored */
	Alp		= 0x08000000,	/* Accept Long Packets */
	Rxfd		= 0x10000000,	/* Receive Full Duplex */
	Stripcrc	= 0x20000000,	/* Strip CRC */
	Arp		= 0x40000000,	/* Accept Runt Packets */
	Aep		= 0x80000000,	/* Accept Errored Packets */
};

enum {					/* Priority Queueing Control */
	Txpqen		= 0x00000001,	/* Transmit Priority Queuing Enable */
	Txfairen	= 0x00000002,	/* Transmit Fairness Enable */
	RxpqenSHFT	= 2,		/* Receive Priority Queue Enable */
	RxpqenMASK	= 0x0000000C,
};

enum {					/* Pause Control/Status */
	PscntSHFT	= 0,		/* Pause Counter Value */
	PscntMASK	= 0x0000FFFF,
	Pstx		= 0x00020000,	/* Transmit Pause Frame */
	PsffloSHFT	= 18,		/* Rx Data FIFO Lo Threshold */
	PsffloMASK	= 0x000C0000,
	PsffhiSHFT	= 20,		/* Rx Data FIFO Hi Threshold */
	PsffhiMASK	= 0x00300000,
	PsstloSHFT	= 22,		/* Rx Stat FIFO Hi Threshold */
	PsstloMASK	= 0x00C00000,
	PssthiSHFT	= 24,		/* Rx Stat FIFO Hi Threshold */
	PssthiMASK	= 0x03000000,
	Psrcvd		= 0x08000000,	/* Pause Frame Received */
	Psact		= 0x10000000,	/* Pause Active */
	Psda		= 0x20000000,	/* Pause on Destination Address */
	Psmcast		= 0x40000000,	/* Pause on Multicast */
	Psen		= 0x80000000,	/* Pause Enable */
};

enum {					/* Receive Filter/Match Control */
	RfaddrSHFT	= 0,		/* Extended Register Address */
	RfaddrMASK	= 0x000003FF,
	Ulm		= 0x00080000,	/* U/L bit mask */
	Uhen		= 0x00100000,	/* Unicast Hash Enable */
	Mhen		= 0x00200000,	/* Multicast Hash Enable */
	Aarp		= 0x00400000,	/* Accept ARP Packets */
	ApatSHFT	= 23,		/* Accept on Pattern Match */
	ApatMASK	= 0x07800000,
	Apm		= 0x08000000,	/* Accept on Perfect Match */
	Aau		= 0x10000000,	/* Accept All Unicast */
	Aam		= 0x20000000,	/* Accept All Multicast */
	Aab		= 0x40000000,	/* Accept All Broadcast */
	Rfen		= 0x80000000,	/* Rx Filter Enable */
};

enum {					/* Receive Filter/Match Data */
	RfdataSHFT	= 0,		/* Receive Filter Data */
	RfdataMASK	= 0x0000FFFF,
	BmaskSHFT	= 16,		/* Byte Mask */
	BmaskMASK	= 0x00030000,
};

enum {					/* MIB Control */
	Wrn		= 0x00000001,	/* Warning Test Indicator */
	Frz		= 0x00000002,	/* Freeze All Counters */
	Aclr		= 0x00000004,	/* Clear All Counters */
	Mibs		= 0x00000008,	/* MIB Counter Strobe */
};

enum {					/* MIB Data */
	Nmibd		= 11,		/* Number of MIB Data Registers */
};

enum {					/* VLAN/IP Receive Control */
	Vtden		= 0x00000001,	/* VLAN Tag Detection Enable */
	Vtren		= 0x00000002,	/* VLAN Tag Removal Enable */
	Dvtf		= 0x00000004,	/* Discard VLAN Tagged Frames */
	Dutf		= 0x00000008,	/* Discard Untagged Frames */
	Ipen		= 0x00000010,	/* IP Checksum Enable */
	Ripe		= 0x00000020,	/* Reject IP Checksum Errors */
	Rtcpe		= 0x00000040,	/* Reject TCP Checksum Errors */
	Rudpe		= 0x00000080,	/* Reject UDP Checksum Errors */
};

enum {					/* VLAN/IP Transmit Control */
	Vgti		= 0x00000001,	/* VLAN Global Tag Insertion */
	Vppti		= 0x00000002,	/* VLAN Per-Packet Tag Insertion */
	Gchk		= 0x00000004,	/* Global Checksum Generation */
	Ppchk		= 0x00000008,	/* Per-Packet Checksum Generation */
};

enum {					/* VLAN Data */
	VtypeSHFT	= 0,		/* VLAN Type Field */
	VtypeMASK	= 0x0000FFFF,
	VtciSHFT	= 16,		/* VLAN Tag Control Information */
	VtciMASK	= 0xFFFF0000,
};

enum {					/* Clockrun Control/Status */
	Clkrunen	= 0x00000001,	/* CLKRUN Enable */
	Pmeen		= 0x00000100,	/* PME Enable */
	Pmests		= 0x00008000,	/* PME Status */
};

typedef struct {
	u32int	link;			/* Link to the next descriptor */
	u32int	bufptr;			/* pointer to data Buffer */
	int	cmdsts;			/* Command/Status */
	int	extsts;			/* optional Extended Status */

	Block*	bp;			/* Block containing bufptr */
	u32int	unused;			/* pad to 64-bit */
} Desc;

enum {					/* Common cmdsts bits */
	SizeMASK	= 0x0000FFFF,	/* Descriptor Byte Count */
	SizeSHFT	= 0,
	Ok		= 0x08000000,	/* Packet OK */
	Crc		= 0x10000000,	/* Suppress/Include CRC */
	Intr		= 0x20000000,	/* Interrupt on ownership transfer */
	More		= 0x40000000,	/* not last descriptor in a packet */
	Own		= 0x80000000,	/* Descriptor Ownership */
};

enum {					/* Transmit cmdsts bits */
	CcntMASK	= 0x000F0000,	/* Collision Count */
	CcntSHFT	= 16,
	Ec		= 0x00100000,	/* Excessive Collisions */
	Owc		= 0x00200000,	/* Out of Window Collision */
	Ed		= 0x00400000,	/* Excessive Deferral */
	Td		= 0x00800000,	/* Transmit Deferred */
	Crs		= 0x01000000,	/* Carrier Sense Lost */
	Tfu		= 0x02000000,	/* Transmit FIFO Underrun */
	Txa		= 0x04000000,	/* Transmit Abort */
};

enum {					/* Receive cmdsts bits */
	Irl		= 0x00010000,	/* In-Range Length Error */
	Lbp		= 0x00020000,	/* Loopback Packet */
	Fae		= 0x00040000,	/* Frame Alignment Error */
	Crce		= 0x00080000,	/* CRC Error */
	Ise		= 0x00100000,	/* Invalid Symbol Error */
	Runt		= 0x00200000,	/* Runt Packet Received */
	Long		= 0x00400000,	/* Too Long Packet Received */
	DestMASK	= 0x01800000,	/* Destination Class */
	DestSHFT	= 23,
	Rxo		= 0x02000000,	/* Receive Overrun */
	Rxa		= 0x04000000,	/* Receive Aborted */
};

enum {					/* extsts bits */
	EvtciMASK	= 0x0000FFFF,	/* VLAN Tag Control Information */
	EvtciSHFT	= 0,
	Vpkt		= 0x00010000,	/* VLAN Packet */
	/* Ippkt, Udppkt are struct types in the fs kernel */
	Ippacket	= 0x00020000,	/* IP Packet */
	Iperr		= 0x00040000,	/* IP Checksum Error */
	Tcppkt		= 0x00080000,	/* TCP Packet */
	Tcperr		= 0x00100000,	/* TCP Checksum Error */
	Udppacket	= 0x00200000,	/* UDP Packet */
	Udperr		= 0x00400000,	/* UDP Checksum Error */
};

/*
 * adjust these, keeping in mind that at 1Gb/s, a 1514-byte packet is
 * sent or received in 12µs.  Ignoring mandatory inter-packet gaps,
 * a ring of 32 buffers will take 388µs to fill or empty; 64 buffers
 * will take 775µs; 256 will take 3.1ms.
 */
enum {
	Nrd		= 64,		// was 64 then 450
	Nrb		= 4*Nrd,
	Rbsz		= ROUNDUP(sizeof(Etherpkt)+8, 8),
	Ntd		= Nrd,		// was 32 then 450
};

typedef struct Ctlr Ctlr;
typedef struct Ctlr {
	int	port;
	Pcidev*	pcidev;
	Ctlr*	next;
	int	active;
	int	id;

	int	eepromsz;		/* address size in bits */
	ushort*	eeprom;

	int*	nic;
	int	cfg;
	int	imr;

	QLock	alock;			/* attach */
	Lock	ilock;			/* init */
	void*	alloc;			/* base of per-Ctlr allocated data */

	Mii*	mii;

	Lock	rdlock;			/* receive */
	Desc*	rd;
	int	nrd;
	int	nrb;
	int	rdx;
	int	rxcfg;

	Lock	tlock;			/* transmit */
	Desc*	td;
	int	ntd;
	int	tdh;
	int	tdt;
	int	ntq;
	int	txcfg;

	int	rxidle;

	uint	mibd[Nmibd];

	int	ec;
	int	owc;
	int	ed;
	int	crs;
	int	tfu;
	int	txa;
} Ctlr;

#define csr32r(c, r)	(*((c)->nic+((r)/4)))
#define csr32w(c, r, v)	(*((c)->nic+((r)/4)) = (v))

static Ctlr* dp83820ctlrhead;
static Ctlr* dp83820ctlrtail;

static Lock dp83820rblock;		/* free receive Blocks */
static Block* dp83820rbpool;

static char* dp83820mibs[Nmibd] = {
	"RXErroredPkts",
	"RXFCSErrors",
	"RXMsdPktErrors",
	"RXFAErrors",
	"RXSymbolErrors",
	"RXFrameToLong",
	"RXIRLErrors",
	"RXBadOpcodes",
	"RXPauseFrames",
	"TXPauseFrames",
	"TXSQEErrors",
};

static int
mdior(Ctlr* ctlr, int n)
{
	int data, i, mear, r;

	mear = csr32r(ctlr, Mear);
	r = ~(Mdc|Mddir) & mear;
	data = 0;
	for(i = n-1; i >= 0; i--){