📄 2db.c

📁 这是一个同样来自贝尔实验室的和UNIX有着渊源的操作系统, 其简洁的设计和实现易于我们学习和理解
💻 C
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{ 0x4180, 0xf1c0, 0x0000, 0x0000, {EADI_W},	"CHKW	%e,R%x" },{ 0x41c0, 0xf1c0, 0x0000, 0x0000, {EAC},	"LEA	%e,A%x" },{ 0x4100, 0xf1c0, 0x0000, 0x0000, {EADI_L},	"CHKL	%e,R%x" },{ 0,0,0,0,{0},0 },};	/* class 5:  miscellaneous quick, branch & trap instructions */static Optable t5[] = {{ 0x5000, 0xf1c0, 0x0000, 0x0000, {EADA},	"ADDB	$Q#%q,%e" },{ 0x5100, 0xf1c0, 0x0000, 0x0000, {EADA},	"SUBB	$Q#%q,%e" },{ 0x50c8, 0xf1f8, 0x0000, 0x0000, {BR16},	"DB%c	R%y,%t" },{ 0x51c8, 0xf1f8, 0x0000, 0x0000, {BR16},	"DB%c	R%y,%t" },{ 0x5000, 0xf1c0, 0x0000, 0x0000, {EAA},	"ADDB	$Q#%q,%e" },{ 0x5040, 0xf1c0, 0x0000, 0x0000, {EAA},	"ADDW	$Q#%q,%e" },{ 0x5080, 0xf1c0, 0x0000, 0x0000, {EAA},	"ADDL	$Q#%q,%e" },{ 0x5100, 0xf1c0, 0x0000, 0x0000, {EAA},	"SUBB	$Q#%q,%e" },{ 0x5140, 0xf1c0, 0x0000, 0x0000, {EAA},	"SUBW	$Q#%q,%e" },{ 0x5180, 0xf1c0, 0x0000, 0x0000, {EAA},	"SUBL	$Q#%q,%e" },{ 0x50fa, 0xf0ff, 0x0000, 0x0000, {I16},	"TRAP%cW	%i" },{ 0x50fb, 0xf0ff, 0x0000, 0x0000, {I32},	"TRAP%cL	%i" },{ 0x50fc, 0xf0ff, 0x0000, 0x0000, {0},		"TRAP%c" },{ 0x50c0, 0xf0c0, 0x0000, 0x0000, {EADA},	"S%c	%e" },{ 0,0,0,0,{0},0 },};	/* class 6: branch instructions */static Optable t6[] = {{ 0x6000, 0xff00, 0x0000, 0x0000, {BR8},	"BRA	%t" },{ 0x6100, 0xff00, 0x0000, 0x0000, {BR8},	"BSR	%t" },{ 0x6000, 0xf000, 0x0000, 0x0000, {BR8},	"B%c	%t" },{ 0,0,0,0,{0},0 },};	/* class 7: move quick */static Optable t7[] = {{ 0x7000, 0xf100, 0x0000, 0x0000, {OP8},	"MOVL	$Q%i,R%x" },{ 0,0,0,0,{0},0 },};	/* class 8: BCD operations, DIV, and OR instructions */static Optable t8[] = {{ 0x8100, 0xf1f8, 0x0000, 0x0000, {0},		"SBCDB	R%y,R%x" },{ 0x8108, 0xf1f8, 0x0000, 0x0000, {0},		"SBCDB	-(A%y),-(A%x)" },{ 0x8140, 0xf1f8, 0x0000, 0x0000, {I16},	"PACK	R%y,R%x,%i" },{ 0x8148, 0xf1f8, 0x0000, 0x0000, {I16},	"PACK	-(A%y),-(A%x),%i" },{ 0x8180, 0xf1f8, 0x0000, 0x0000, {I16},	"UNPK	R%y,R%x,%i" },{ 0x8188, 0xf1f8, 0x0000, 0x0000, {I16},	"UNPK	-(A%y),-(A%x),%i" },{ 0x80c0, 0xf1c0, 0x0000, 0x0000, {EADI_W},	"DIVUW	%e,R%x" },{ 0x81c0, 0xf1c0, 0x0000, 0x0000, {EADI_W},	"DIVSW	%e,R%x" },{ 0x8000, 0xf100, 0x0000, 0x0000, {EADI},	"OR%s	%e,R%x" },{ 0x8100, 0xf100, 0x0000, 0x0000, {EAMA},	"OR%s	R%x,%e" },{ 0,0,0,0,{0},0 },};	/* class 9: subtract instruction */static Optable t9[] = {{ 0x90c0, 0xf1c0, 0x0000, 0x0000, {EAALL_W},	"SUBW	%e,A%x" },{ 0x91c0, 0xf1c0, 0x0000, 0x0000, {EAALL_L},	"SUBL	%e,A%x" },{ 0x9100, 0xf138, 0x0000, 0x0000, {0},		"SUBX%s	R%y,R%x" },{ 0x9108, 0xf138, 0x0000, 0x0000, {0},		"SUBX%s	-(A%y),-(A%x)" },{ 0x9000, 0xf100, 0x0000, 0x0000, {EAALL},	"SUB%s	%e,R%x" },{ 0x9100, 0xf100, 0x0000, 0x0000, {EAMA},	"SUB%s	R%x,%e" },{ 0,0,0,0,{0},0 },};	/* class b: CMP & EOR */static Optable tb[] = {{ 0xb000, 0xf1c0, 0x0000, 0x0000, {EADI},	"CMPB	R%x,%e" },{ 0xb040, 0xf1c0, 0x0000, 0x0000, {EAALL_W},	"CMPW	R%x,%e" },{ 0xb080, 0xf1c0, 0x0000, 0x0000, {EAALL_L},	"CMPL	R%x,%e" },{ 0xb0c0, 0xf1c0, 0x0000, 0x0000, {EAALL_W},	"CMPW	A%x,%e" },{ 0xb1c0, 0xf1c0, 0x0000, 0x0000, {EAALL_L},	"CMPL	A%x,%e" },{ 0xb108, 0xf138, 0x0000, 0x0000, {0},		"CMP%s	(A%y)+,(A%x)+" },{ 0xb100, 0xf100, 0x0000, 0x0000, {EADA},	"EOR%s	%e,R%x" },{ 0,0,0,0,{0},0 },};	/* class c: AND, MUL, BCD & Exchange */static Optable tc[] = {{ 0xc100, 0xf1f8, 0x0000, 0x0000, {0},		"ABCDB	R%y,R%x" },{ 0xc108, 0xf1f8, 0x0000, 0x0000, {0},		"ABCDB	-(A%y),-(A%x)" },{ 0xc140, 0xf1f8, 0x0000, 0x0000, {0},		"EXG	R%x,R%y" },{ 0xc148, 0xf1f8, 0x0000, 0x0000, {0},		"EXG	A%x,A%y" },{ 0xc188, 0xf1f8, 0x0000, 0x0000, {0},		"EXG	R%x,A%y" },{ 0xc0c0, 0xf1c0, 0x0000, 0x0000, {EADI_W},	"MULUW	%e,R%x" },{ 0xc1c0, 0xf1c0, 0x0000, 0x0000, {EADI_W},	"MULSW	%e,R%x" },{ 0xc000, 0xf100, 0x0000, 0x0000, {EADI},	"AND%s	%e,R%x" },{ 0xc100, 0xf100, 0x0000, 0x0000, {EAMA},	"AND%s	R%x,%e" },{ 0,0,0,0,{0},0 },};	/* class d: addition  */static Optable td[] = {{ 0xd000, 0xf1c0, 0x0000, 0x0000, {EADI},	"ADDB	%e,R%x" },{ 0xd0c0, 0xf1c0, 0x0000, 0x0000, {EAALL_W},	"ADDW	%e,A%x" },{ 0xd1c0, 0xf1c0, 0x0000, 0x0000, {EAALL_L},	"ADDL	%e,A%x" },{ 0xd100, 0xf138, 0x0000, 0x0000, {0},		"ADDX%s	R%y,R%x" },{ 0xd108, 0xf138, 0x0000, 0x0000, {0},		"ADDX%s	-(A%y),-(A%x)" },{ 0xd000, 0xf100, 0x0000, 0x0000, {EAALL},	"ADD%s	%e,R%x" },{ 0xd100, 0xf100, 0x0000, 0x0000, {EAMA},	"ADD%s	R%x,%e" },{ 0,0,0,0,{0},0 },};	/* class e: shift, rotate, bit field operations */static Optable te[] = {{ 0xe8c0, 0xffc0, 0x0820, 0xfe38, {EACD},	"BFTST	%e{R%u:R%a}" },{ 0xe8c0, 0xffc0, 0x0800, 0xfe20, {EACD},	"BFTST	%e{R%u:%w}" },{ 0xe8c0, 0xffc0, 0x0020, 0xf838, {EACD},	"BFTST	%e{%o:R%a}" },{ 0xe8c0, 0xffc0, 0x0000, 0xf820, {EACD},	"BFTST	%e{%o:%w}" },{ 0xe9c0, 0xffc0, 0x0820, 0x8e38, {EACD},	"BFEXTU	%e{R%u:R%a},%r" },{ 0xe9c0, 0xffc0, 0x0800, 0x8e20, {EACD},	"BFEXTU	%e{R%u:%w},%r" },{ 0xe9c0, 0xffc0, 0x0020, 0x8838, {EACD},	"BFEXTU	%e{%o:R%a},%r" },{ 0xe9c0, 0xffc0, 0x0000, 0x8820, {EACD},	"BFEXTU	%e{%o:%w},%r" },{ 0xeac0, 0xffc0, 0x0820, 0xfe38, {EACAD},	"BFCHG	%e{R%u:R%a}" },{ 0xeac0, 0xffc0, 0x0800, 0xfe20, {EACAD},	"BFCHG	%e{R%u:%w}" },{ 0xeac0, 0xffc0, 0x0020, 0xf838, {EACAD},	"BFCHG	%e{%o:R%a}" },{ 0xeac0, 0xffc0, 0x0000, 0xf820, {EACAD},	"BFCHG	%e{%o:%w}" },{ 0xebc0, 0xffc0, 0x0820, 0x8e38, {EACD},	"BFEXTS	%e{R%u:R%a},%r" },{ 0xebc0, 0xffc0, 0x0800, 0x8e20, {EACD},	"BFEXTS	%e{R%u:%w},%r" },{ 0xebc0, 0xffc0, 0x0020, 0x8838, {EACD},	"BFEXTS	%e{%o:R%a},%r" },{ 0xebc0, 0xffc0, 0x0000, 0x8820, {EACD},	"BFEXTS	%e{%o:%w},%r" },{ 0xecc0, 0xffc0, 0x0820, 0xfe38, {EACAD},	"BFCLR	%e{R%u:R%a}" },{ 0xecc0, 0xffc0, 0x0800, 0xfe20, {EACAD},	"BFCLR	%e{R%u:%w}" },{ 0xecc0, 0xffc0, 0x0020, 0xf838, {EACAD},	"BFCLR	%e{%o:R%a}" },{ 0xecc0, 0xffc0, 0x0000, 0xf820, {EACAD},	"BFCLR	%e{%o:%w}" },{ 0xedc0, 0xffc0, 0x0820, 0x8e38, {EACAD},	"BFFFO	%e{R%u:R%a},%r" },{ 0xedc0, 0xffc0, 0x0800, 0x8e20, {EACAD},	"BFFFO	%e{R%u:%w},%r" },{ 0xedc0, 0xffc0, 0x0020, 0x8838, {EACAD},	"BFFFO	%e{%o:R%a},%r" },{ 0xedc0, 0xffc0, 0x0000, 0x8820, {EACAD},	"BFFFO	%e{%o:%w},%r" },{ 0xeec0, 0xffc0, 0x0820, 0xfe38, {EACAD},	"BFSET	%e{R%u:R%a}" },{ 0xeec0, 0xffc0, 0x0800, 0xfe20, {EACAD},	"BFSET	%e{R%u:%w}" },{ 0xeec0, 0xffc0, 0x0020, 0xf838, {EACAD},	"BFSET	%e{%o:R%a}" },{ 0xeec0, 0xffc0, 0x0000, 0xf820, {EACAD},	"BFSET	%e{%o:%w}" },{ 0xefc0, 0xffc0, 0x0820, 0x8e38, {EACAD},	"BFINS	%r,%e{R%u:R%a}" },{ 0xefc0, 0xffc0, 0x0800, 0x8e20, {EACAD},	"BFINS	%r,%e{R%u:%w}" },{ 0xefc0, 0xffc0, 0x0020, 0x8838, {EACAD},	"BFINS	%r,%e{%o:R%a}" },{ 0xefc0, 0xffc0, 0x0000, 0x8820, {EACAD},	"BFINS	%r,%e{%o:%w}" },{ 0xe0c0, 0xfec0, 0x0000, 0x0000, {EAMA},	"AS%dW	%e" },{ 0xe2c0, 0xfec0, 0x0000, 0x0000, {EAMA},	"LS%dW	%e" },{ 0xe4c0, 0xfec0, 0x0000, 0x0000, {EAMA},	"ROX%dW	%e" },{ 0xe6c0, 0xfec0, 0x0000, 0x0000, {EAMA},	"RO%dW	%e" },{ 0xe000, 0xf038, 0x0000, 0x0000, {0},		"AS%d%s	#%q,R%y" },{ 0xe008, 0xf038, 0x0000, 0x0000, {0},		"LS%d%s	#%q,R%y" },{ 0xe010, 0xf038, 0x0000, 0x0000, {0},		"ROX%d%s	#%q,R%y" },{ 0xe018, 0xf038, 0x0000, 0x0000, {0},		"RO%d%s	#%q,R%y" },{ 0xe020, 0xf038, 0x0000, 0x0000, {0},		"AS%d%s	R%x,R%y" },{ 0xe028, 0xf038, 0x0000, 0x0000, {0},		"LS%d%s	R%x,R%y" },{ 0xe030, 0xf038, 0x0000, 0x0000, {0},		"ROX%d%s	R%x,R%y" },{ 0xe038, 0xf038, 0x0000, 0x0000, {0},		"RO%d%s	R%x,R%y" },{ 0,0,0,0,{0},0 },};	/* class f: coprocessor and mmu instructions */static Optable tf[] = {{ 0xf280, 0xffff, 0x0000, 0xffff, {0},		"FNOP" },{ 0xf200, 0xffff, 0x5c00, 0xfc00, {0},		"FMOVECRX	%k,F%D" },{ 0xf27a, 0xffff, 0x0000, 0xffc0, {I16},	"FTRAP%P	%i" },{ 0xf27b, 0xffff, 0x0000, 0xffc0, {I32},	"FTRAP%P	%i" },{ 0xf27c, 0xffff, 0x0000, 0xffc0, {0},		"FTRAP%P" },{ 0xf248, 0xfff8, 0x0000, 0xffc0, {BR16},	"FDB%P	R%y,%t" },{ 0xf620, 0xfff8, 0x8000, 0x8fff, {0},		"MOVE16	(A%y)+,(%r)+" },{ 0xf500, 0xfff8, 0x0000, 0x0000, {0},		"PFLUSHN	(A%y)" },{ 0xf508, 0xfff8, 0x0000, 0x0000, {0},		"PFLUSH	(A%y)" },{ 0xf510, 0xfff8, 0x0000, 0x0000, {0},		"PFLUSHAN" },{ 0xf518, 0xfff8, 0x0000, 0x0000, {0},		"PFLUSHA" },{ 0xf548, 0xfff8, 0x0000, 0x0000, {0},		"PTESTW	(A%y)" },{ 0xf568, 0xfff8, 0x0000, 0x0000, {0},		"PTESTR	(A%y)" },{ 0xf600, 0xfff8, 0x0000, 0x0000, {I32},	"MOVE16	(A%y)+,$%i" },{ 0xf608, 0xfff8, 0x0000, 0x0000, {I32},	"MOVE16	$%i,(A%y)-" },{ 0xf610, 0xfff8, 0x0000, 0x0000, {I32},	"MOVE16	(A%y),$%i" },{ 0xf618, 0xfff8, 0x0000, 0x0000, {I32},	"MOVE16	$%i,(A%y)" },{ 0xf000, 0xffc0, 0x0800, 0xffff, {EACA},	"PMOVE	%e,TT0" },{ 0xf000, 0xffc0, 0x0900, 0xffff, {EACA},	"PMOVEFD	%e,TT0" },{ 0xf000, 0xffc0, 0x0a00, 0xffff, {EACA},	"PMOVE	TT0,%e" },{ 0xf000, 0xffc0, 0x0b00, 0xffff, {EACA},	"PMOVEFD	TT0,%e" },{ 0xf000, 0xffc0, 0x0c00, 0xffff, {EACA},	"PMOVE	%e,TT1" },{ 0xf000, 0xffc0, 0x0d00, 0xffff, {EACA},	"PMOVEFD	%e,TT1" },{ 0xf000, 0xffc0, 0x0e00, 0xffff, {EACA},	"PMOVE	TT1,%e" },{ 0xf000, 0xffc0, 0x0f00, 0xffff, {EACA},	"PMOVEFD	TT1,%e" },{ 0xf000, 0xffc0, 0x2400, 0xffff, {0},		"PFLUSHA" },{ 0xf000, 0xffc0, 0x2800, 0xffff, {EACA},	"PVALID	VAL,%e" },{ 0xf000, 0xffc0, 0x6000, 0xffff, {EACA},	"PMOVE	%e,MMUSR" },{ 0xf000, 0xffc0, 0x6200, 0xffff, {EACA},	"PMOVE	MMUSR,%e" },{ 0xf000, 0xffc0, 0x2800, 0xfff8, {EACA},	"PVALID	A%a,%e" },{ 0xf000, 0xffc0, 0x2000, 0xffe0, {EACA},	"PLOADW	%L,%e" },{ 0xf000, 0xffc0, 0x2200, 0xffe0, {EACA},	"PLOADR	%L,%e" },{ 0xf000, 0xffc0, 0x8000, 0xffe0, {EACA},	"PTESTW	%L,%e,#0" },{ 0xf000, 0xffc0, 0x8200, 0xffe0, {EACA},	"PTESTR	%L,%e,#0" },{ 0xf000, 0xffc0, 0x3000, 0xfe00, {0},		"PFLUSH	%L,#%I" },{ 0xf000, 0xffc0, 0x3800, 0xfe00, {EACA},	"PFLUSH	%L,#%I,%e" },{ 0xf000, 0xffc0, 0x8000, 0xe300, {EACA},	"PTESTW	%L,%e,#%Z" },{ 0xf000, 0xffc0, 0x8100, 0xe300, {EACA},	"PTESTW	%L,%e,#%Z,A%h" },{ 0xf000, 0xffc0, 0x8200, 0xe300, {EACA},	"PTESTR	%L,%e,#%Z" },{ 0xf000, 0xffc0, 0x8300, 0xe300, {EACA},	"PTESTR	%L,%e,#%Z,A%h" },{ 0xf000, 0xffc0, 0x4000, 0xc3ff, {EACA},	"PMOVE	%e,%H" },{ 0xf000, 0xffc0, 0x4100, 0xc3ff, {EACA},	"PMOVEFD	%e,%H" },{ 0xf000, 0xffc0, 0x4200, 0xc3ff, {EACA},	"PMOVE	%H,%e" },	/* floating point (coprocessor 1)*/{ 0xf200, 0xffc0, 0x8400, 0xffff, {EAALL_L},	"FMOVEL	%e,FPIAR" },{ 0xf200, 0xffc0, 0x8800, 0xffff, {EADI_L},	"FMOVEL	%e,FPSR" },{ 0xf200, 0xffc0, 0x9000, 0xffff, {EADI_L},	"FMOVEL	%e,FPCR" },{ 0xf200, 0xffc0, 0xa400, 0xffff, {EAA},	"FMOVEL	FPIAR,%e" },{ 0xf200, 0xffc0, 0xa800, 0xffff, {EADA},	"FMOVEL	FPSR,%e" },{ 0xf200, 0xffc0, 0xb000, 0xffff, {EADA},	"FMOVEL	FPCR,%e" },{ 0xf240, 0xffc0, 0x0000, 0xffc0, {EADA},	"FS%P	%e" },{ 0xf200, 0xffc0, 0xd000, 0xff00, {EACPI},	"FMOVEMX	%e,%m" },{ 0xf200, 0xffc0, 0xd800, 0xff00, {EACPI},	"FMOVEMX	%e,R%K" },{ 0xf200, 0xffc0, 0xe000, 0xff00, {EAPI},	"FMOVEMX	%m,-(A%y)" },{ 0xf200, 0xffc0, 0xe800, 0xff00, {EAPI},	"FMOVEMX	R%K,-(A%y)" },{ 0xf200, 0xffc0, 0xf000, 0xff00, {EACAPD},	"FMOVEMX	%m,%e" },{ 0xf200, 0xffc0, 0xf800, 0xff00, {EACAPD},	"FMOVEMX	R%K,%e" },{ 0xf200, 0xffc0, 0x6800, 0xfc00, {EAMA},	"FMOVEX	F%D,%e" },{ 0xf200, 0xffc0, 0x6c00, 0xfc00, {EAMA},	"FMOVEP	F%D,%e,{%k}" },{ 0xf200, 0xffc0, 0x7400, 0xfc00, {EAMA},	"FMOVED	F%D,%e" },{ 0xf200, 0xffc0, 0x7c00, 0xfc00, {EAMA},	"FMOVEP	F%D,%e,{R%K}" },{ 0xf200, 0xffc0, 0x8000, 0xe3ff, {EAM},	"FMOVEML	#%B,%e" },{ 0xf200, 0xffc0, 0xa000, 0xe3ff, {EAMA},	"FMOVEML	%e,#%B" },{ 0xf200, 0xffc0, 0x0000, 0xe07f, {0},		"FMOVE	F%B,F%D" },{ 0xf200, 0xffc0, 0x0001, 0xe07f, {0},		"FINTX	%F" },{ 0xf200, 0xffc0, 0x0002, 0xe07f, {0},		"FSINHX	%F" },{ 0xf200, 0xffc0, 0x0003, 0xe07f, {0},		"FINTRZ	%F" },{ 0xf200, 0xffc0, 0x0004, 0xe07f, {0},		"FSQRTX	%F" },{ 0xf200, 0xffc0, 0x0006, 0xe07f, {0},		"FLOGNP1X	%F" },{ 0xf200, 0xffc0, 0x0009, 0xe07f, {0},		"FTANHX	%F" },{ 0xf200, 0xffc0, 0x000a, 0xe07f, {0},		"FATANX	%F" },{ 0xf200, 0xffc0, 0x000c, 0xe07f, {0},		"FASINX	%F" },{ 0xf200, 0xffc0, 0x000d, 0xe07f, {0},		"FATANHX	%F" },{ 0xf200, 0xffc0, 0x000e, 0xe07f, {0},		"FSINX	%F" },{ 0xf200, 0xffc0, 0x000f, 0xe07f, {0},		"FTANX	%F" },{ 0xf200, 0xffc0, 0x0010, 0xe07f, {0},		"FETOXX	%F" },{ 0xf200, 0xffc0, 0x0011, 0xe07f, {0},		"FTWOTOXX	%F" },{ 0xf200, 0xffc0, 0x0012, 0xe07f, {0},		"FTENTOXX	%F" },{ 0xf200, 0xffc0, 0x0014, 0xe07f, {0},		"FLOGNX	%F" },{ 0xf200, 0xffc0, 0x0015, 0xe07f, {0},		"FLOG10X	%F" },{ 0xf200, 0xffc0, 0x0016, 0xe07f, {0},		"FLOG2X	%F" },{ 0xf200, 0xffc0, 0x0018, 0xe07f, {0},		"FABSX	%F" },{ 0xf200, 0xffc0, 0x0019, 0xe07f, {0},		"FCOSHX	%F" },{ 0xf200, 0xffc0, 0x001a, 0xe07f, {0},		"FNEGX	%F" },{ 0xf200, 0xffc0, 0x001c, 0xe07f, {0},		"FACOSX	%F" },{ 0xf200, 0xffc0, 0x001d, 0xe07f, {0},		"FCOSX	%F" },{ 0xf200, 0xffc0, 0x001e, 0xe07f, {0},		"FGETEXPX	%F" },{ 0xf200, 0xffc0, 0x001f, 0xe07f, {0},		"FGETMANX	%F" },{ 0xf200, 0xffc0, 0x0020, 0xe07f, {0},		"FDIVX	F%B,F%D" },{ 0xf200, 0xffc0, 0x0021, 0xe07f, {0},		"FMODX	F%B,F%D" },{ 0xf200, 0xffc0, 0x0022, 0xe07f, {0},		"FADDX	F%B,F%D" },{ 0xf200, 0xffc0, 0x0023, 0xe07f, {0},		"FMULX	F%B,F%D" },{ 0xf200, 0xffc0, 0x0024, 0xe07f, {0},		"FSGLDIVX	F%B,F%D" },{ 0xf200, 0xffc0, 0x0025, 0xe07f, {0},		"FREMX	F%B,F%D" },{ 0xf200, 0xffc0, 0x0026, 0xe07f, {0},		"FSCALEX	F%B,F%D" },{ 0xf200, 0xffc0, 0x0027, 0xe07f, {0},		"FSGLMULX	F%B,F%D" },{ 0xf200, 0xffc0, 0x0028, 0xe07f, {0},		"FSUBX	F%B,F%D" },{ 0xf200, 0xffc0, 0x0038, 0xe07f, {0},		"FCMPX	F%B,F%D" },{ 0xf200, 0xffc0, 0x003a, 0xe07f, {0},		"FTSTX	F%B" },{ 0xf200, 0xffc0, 0x0040, 0xe07f, {0},		"FSMOVE	F%B,F%D" },{ 0xf200, 0xffc0, 0x0041, 0xe07f, {0},		"FSSQRTX	%F"},{ 0xf200, 0xffc0, 0x0044, 0xe07f, {0},		"FDMOVE	F%B,F%D" },{ 0xf200, 0xffc0, 0x0045, 0xe07f, {0},		"FDSQRTX	%F" },{ 0xf200, 0xffc0, 0x0058, 0xe07f, {0},		"FSABSX	%F" },{ 0xf200, 0xffc0, 0x005a, 0xe07f, {0},		"FSNEGX	%F" },{ 0xf200, 0xffc0, 0x005c, 0xe07f, {0},		"FDABSX	%F" },{ 0xf200, 0xffc0, 0x005e, 0xe07f, {0},		"FDNEGX	%F" },{ 0xf200, 0xffc0, 0x0060, 0xe07f, {0},		"FSDIVX	F%B,F%D" },{ 0xf200, 0xffc0, 0x0062, 0xe07f, {0},		"FSADDX	F%B,F%D" },{ 0xf200, 0xffc0, 0x0063, 0xe07f, {0},		"FSMULX	F%B,F%D" },{ 0xf200, 0xffc0, 0x0064, 0xe07f, {0},		"FDDIVX	F%B,F%D" },{ 0xf200, 0xffc0, 0x0066, 0xe07f, {0},		"FDADDX	F%B,F%D" },{ 0xf200, 0xffc0, 0x0067, 0xe07f, {0},		"FDMULX	F%B,F%D" },{ 0xf200, 0xffc0, 0x0068, 0xe07f, {0},		"FSSUBX	F%B,F%D" },{ 0xf200, 0xffc0, 0x006c, 0xe07f, {0},		"FDSUBX	F%B,F%D" },{ 0xf200, 0xffc0, 0x4000, 0xe07f, {EAFLT},	"FMOVE%S	%e,F%D" },{ 0xf200, 0xffc0, 0x4001, 0xe07f, {EAFLT},	"FINT%S	%e,F%D" },{ 0xf200, 0xffc0, 0x4002, 0xe07f, {EAFLT},	"FSINH%S	%e,F%D" },{ 0xf200, 0xffc0, 0x4003, 0xe07f, {EAFLT},	"FINTRZ%S	%e,F%D" },{ 0xf200, 0xffc0, 0x4004, 0xe07f, {EAFLT},	"FSQRT%S	%e,F%D" },{ 0xf200, 0xffc0, 0x4006, 0xe07f, {EAFLT},	"FLOGNP1%S	%e,F%D" },{ 0xf200, 0xffc0, 0x4009, 0xe07f, {EAFLT},	"FTANH%S	%e,F%D" },{ 0xf200, 0xffc0, 0x400a, 0xe07f, {EAFLT},	"FATAN%S	%e,F%D" },{ 0xf200, 0xffc0, 0x400c, 0xe07f, {EAFLT},	"FASIN%S	%e,F%D" },{ 0xf200, 0xffc0, 0x400d, 0xe07f, {EAFLT},	"FATANH%S	%e,F%D" },{ 0xf200, 0xffc0, 0x400e, 0xe07f, {EAFLT},	"FSIN%S	%e,F%D" },{ 0xf200, 0xffc0, 0x400f, 0xe07f, {EAFLT},	"FTAN%S	%e,F%D" },{ 0xf200, 0xffc0, 0x4010, 0xe07f, {EAFLT},	"FETOX%S	%e,F%D" },{ 0xf200, 0xffc0, 0x4011, 0xe07f, {EAFLT},	"FTWOTOX%S	%e,F%D" },{ 0xf200, 0xffc0, 0x4012, 0xe07f, {EAFLT},	"FTENTOX%S	%e,F%D" },{ 0xf200, 0xffc0, 0x4014, 0xe07f, {EAFLT},	"FLOGN%S	%e,F%D" },{ 0xf200, 0xffc0, 0x4015, 0xe07f, {EAFLT},	"FLOG10%S	%e,F%D" },{ 0xf200, 0xffc0, 0x4016, 0xe07f, {EAFLT},	"FLOG2%S	%e,F%D" },{ 0xf200, 0xffc0, 0x4018, 0xe07f, {EAFLT},	"FABS%S	%e,F%D" },{ 0xf200, 0xffc0, 0x4019, 0xe07f, {EAFLT},	"FCOSH%S	%e,F%D" },{ 0xf200, 0xffc0, 0x401a, 0xe07f, {EAFLT},	"FNEG%S	%e,F%D" },{ 0xf200, 0xffc0, 0x401c, 0xe07f, {EAFLT},	"FACOS%S	%e,F%D" },{ 0xf200, 0xffc0, 0x401d, 0xe07f, {EAFLT},	"FCOS%S	%e,F%D" },{ 0xf200, 0xffc0, 0x401e, 0xe07f, {EAFLT},	"FGETEXP%S	%e,F%D" },{ 0xf200, 0xffc0, 0x401f, 0xe07f, {EAFLT},	"FGETMAN%S	%e,F%D" },{ 0xf200, 0xffc0, 0x4020, 0xe07f, {EAFLT},	"FDIV%S	%e,F%D" },{ 0xf200, 0xffc0, 0x4021, 0xe07f, {EAFLT},	"FMOD%S	%e,F%D" },{ 0xf200, 0xffc0, 0x4022, 0xe07f, {EAFLT},	"FADD%S	%e,F%D" },{ 0xf200, 0xffc0, 0x4023, 0xe07f, {EAFLT},	"FMUL%S	%e,F%D" },{ 0xf200, 0xffc0, 0x4024, 0xe07f, {EAFLT},	"FSGLDIV%S	%e,F%D" },{ 0xf200, 0xffc0, 0x4025, 0xe07f, {EAFLT},	"FREM%S	%e,F%D" },{ 0xf200, 0xffc0, 0x4026, 0xe07f, {EAFLT},	"FSCALE%S	%e,F%D" },{ 0xf200, 0xffc0, 0x4027, 0xe07f, {EAFLT},	"FSGLMUL%S	%e,F%D" },{ 0xf200, 0xffc0, 0x4028, 0xe07f, {EAFLT},	"FSUB%S	%e,F%D" },{ 0xf200, 0xffc0, 0x4038, 0xe07f, {EAFLT},	"FCMP%S	%e,F%D" },{ 0xf200, 0xffc0, 0x403a, 0xe07f, {EAFLT},	"FTST%S	%e" },{ 0xf200, 0xffc0, 0x4040, 0xe07f, {EAFLT},	"FSMOVE%S	%e,F%D" },{ 0xf200, 0xffc0, 0x4041, 0xe07f, {EAFLT},	"FSSQRT%S	%e,F%D" },{ 0xf200, 0xffc0, 0x4044, 0xe07f, {EAFLT},	"FDMOVE%S	%e,F%D" },{ 0xf200, 0xffc0, 0x4045, 0xe07f, {EAFLT},	"FDSQRT%S	%e,F%D" },{ 0xf200, 0xffc0, 0x4058, 0xe07f, {EAFLT},	"FSABS%S	%e,F%D" },{ 0xf200, 0xffc0, 0x405a, 0xe07f, {EAFLT},	"FSNEG%S	%e,F%D" },{ 0xf200, 0xffc0, 0x405c, 0xe07f, {EAFLT},	"FDABS%S	%e,F%D" },{ 0xf200, 0xffc0, 0x405e, 0xe07f, {EAFLT},	"FDNEG%S	%e,F%D" },{ 0xf200, 0xffc0, 0x4060, 0xe07f, {EAFLT},	"FSDIV%S	%e,F%D" },{ 0xf200, 0xffc0, 0x4062, 0xe07f, {EAFLT},	"FSADD%S	%e,F%D" },{ 0xf200, 0xffc0, 0x4063, 0xe07f, {EAFLT},	"FSMUL%S	%e,F%D" },{ 0xf200, 0xffc0, 0x4064, 0xe07f, {EAFLT},	"FDDIV%S	%e,F%D" },{ 0xf200, 0xffc0, 0x4066, 0xe07f, {EAFLT},	"FDADD%S	%e,F%D" },{ 0xf200, 0xffc0, 0x4067, 0xe07f, {EAFLT},	"FDMUL%S	%e,F%D" },{ 0xf200, 0xffc0, 0x4068, 0xe07f, {EAFLT},	"FSSUB%S	%e,F%D" },{ 0xf200, 0xffc0, 0x406c, 0xe07f, {EAFLT},	"FDSUB%S	%e,F%D" },{ 0xf200, 0xffc0, 0x0030, 0xe078, {0},		"FSINCOSX	F%B,F%a:F%D" },{ 0xf200, 0xffc0, 0x4030, 0xe078, {EAFLT},	"FSINCOS%S	%e,F%a:F%D" },{ 0xf200, 0xffc0, 0x6000, 0xe000, {EADA},	"FMOVE%S	F%D,%e" },{ 0xf300, 0xffc0, 0x0000, 0x0000, {EACAPD},	"FSAVE	%e" },{ 0xf340, 0xffc0, 0x0000, 0x0000, {EACAPI},	"FRESTORE	%e" },{ 0xf280, 0xffc0, 0x0000, 0x0000, {BR16},	"FB%p	%t" },{ 0xf2c0, 0xffc0, 0x0000, 0x0000, {BR32},	"FB%p	%t" },{ 0xf408, 0xff38, 0x0000, 0x0000, {0},		"CINVL	%C,(A%y)" },{ 0xf410, 0xff38, 0x0000, 0x0000, {0},		"CINVP	%C,(A%y)" },{ 0xf418, 0xff38, 0x0000, 0x0000, {0},		"CINVA	%C" },{ 0xf428, 0xff38, 0x0000, 0x0000, {0},		"CPUSHL	%C,(A%y)" },{ 0xf430, 0xff38, 0x0000, 0x0000, {0},		"CPUSHP	%C,(A%y)" },{ 0xf438, 0xff38, 0x0000, 0x0000, {0},		"CPUSHA	%C" },{ 0,0,0,0,{0},0 },};static Optable	*optables[] ={	t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, 0, tb, tc, td, te, tf,};static	Map	*mymap;static intdumpinst(Inst *ip, char *buf, int n){	int i;	if (n <= 0)		return 0;	*buf++ = '#';	for (i = 0; i < ip->n && i*4+1 < n-4; i++, buf += 4)		_hexify(buf, ip->raw[i], 3);	*buf = 0;	return i*4+1;}static intgetword(Inst *ip, uvlong offset){	if (ip->n < nelem(ip->raw)) {		if (get2(mymap, offset, &ip->raw[ip->n++]) > 0)			return 1;		werrstr("can't read instruction: %r");	} else		werrstr("instruction too big: %r");	return -1;}static intgetshorts(Inst *ip, void *where, int n){	if (ip->n+n < nelem(ip->raw)) {		if (get1(mymap, ip->addr+ip->n*2, (uchar*)&ip->raw[ip->n], n*2) < 0) {			werrstr("can't read instruction: %r");			return 0;		}		memmove(where, &ip->raw[ip->n], n*2);		ip->n += n;		return 1;	}	werrstr("instruction too big: %r");	return 0;}static inti8(Inst *ip, long *l){	if (getword(ip, ip->addr+ip->n*2) < 0)		return -1;	*l = ip->raw[ip->n-1]&0xff;	if (*l&0x80)		*l |= ~0xff;	return 1;}static inti16(Inst *ip, long *l){	if (getword(ip, ip->addr+ip->n*2) < 0)		return -1;	*l = ip->raw[ip->n-1];	if (*l&0x8000)		*l |= ~0xffff;	return 1;}static inti32(Inst *ip, long *l){	if (getword(ip, ip->addr+ip->n*2) < 0)		return -1;	if (getword(ip, ip->addr+ip->n*2) < 0)		return -1;	*l = (ip->raw[ip->n-2]<<16)|ip->raw[ip->n-1];	return 1;}static intgetimm(Inst *ip, Operand *ap, int mode){	ap->eatype = IMM;	switch(mode)	{	case EAM_B:	/* byte */	case EAALL_B:		return i8(ip, &ap->immediate);	case EADI_W:	/* word */	case EAALL_W:		return i16(ip, &ap->immediate);	case EADI_L:	/* long */	case EAALL_L:		return i32(ip, &ap->immediate);	case EAFLT:	/* floating point - size in bits 10-12 or word 1 */		switch((ip->raw[1]>>10)&0x07)		{		case 0:	/* long integer */			return i32(ip, &ap->immediate);		case 1:	/* single precision real */			ap->eatype = IREAL;			return getshorts(ip, ap->floater, 2);		case 2:	/* extended precision real - not supported */			ap->eatype = IEXT;			return getshorts(ip, ap->floater, 6);		case 3: /* packed decimal real - not supported */			ap->eatype = IPACK;			return getshorts(ip, ap->floater, 12);		case 4:	/* integer word */			return i16(ip, &ap->immediate);		case 5:	/* double precision real */			ap->eatype = IDBL;			return getshorts(ip, ap->floater, 4);		case 6:	/* integer byte */			return i8(ip, &ap->immediate);		default:			ip->errmsg = "bad immediate float data";			return -1;		}		/* not reached */	case IV:	/* size encoded in bits 6&7 of opcode word */	default:		switch((ip->raw[0]>>6)&0x03)		{		case 0x00:	/* integer byte */			return i8(ip, &ap->immediate);		case 0x01:	/* integer word */			return i16(ip, &ap->immediate);		case 0x02:	/* integer long */			return i32(ip, &ap->immediate);		default:			ip->errmsg = "bad immediate size";			return -1;		}		/* not reached */	}}static intgetdisp(Inst *ip, Operand *ap){	short ext;	if (getword(ip, ip->addr+ip->n*2) < 0)		return -1;	ext = ip->raw[ip->n-1];	ap->ext = ext;	if ((ext&0x100) == 0) {		/* indexed with 7-bit displacement */		ap->disp = ext&0x7f;		if (ap->disp&0x40)			ap->disp |= ~0x7f;		return 1;	}	switch(ext&0x30)	/* first (inner) displacement  */
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