l.s

这是一个同样来自贝尔实验室的和UNIX有着渊源的操作系统, 其简洁的设计和实现易于我们学习和理解

 * traps force memory mapping off.
 * the following code has been executed at the exception
 * vector location
 *	MOVW	R0, SPR(SAVER0)
 *	MOVW	LR, R0
 *	MOVW	R0, SPR(SAVELR)
 *	bl	trapvec(SB)
 *
 */
TEXT trapvec(SB), $-4
	MOVW	LR, R0
	MOVW	R1, SPR(SAVER1)
	MOVW	R0, SPR(SAVEXX)		/* vector */

	/* did we come from user space */
	MOVW	SPR(SRR1), R0
	MOVW	CR, R1
	MOVW	R0, CR
	BC	4, 17, ktrap

	/* switch to kernel stack */
	MOVW	R1, CR
	MOVW	$MACHPADDR, R1		/* PADDR(m->) */
	MOVW	8(R1), R1		/* m->proc */
	RLWNM	$0, R1, $~KZERO, R1	/* PADDR(m->proc) */
	MOVW	8(R1), R1		/* m->proc->kstack */
	RLWNM	$0, R1, $~KZERO, R1	/* PADDR(m->proc->kstack) */
	ADD	$(KSTACK-UREGSIZE), R1	/* make room on stack */

	BL	saveureg(SB)
	BL	trap(SB)
	BR	restoreureg

ktrap:
	MOVW	R1, CR
	MOVW	SPR(SAVER1), R1
	RLWNM	$0, R1, $~KZERO, R1	/* set stack pointer */
	SUB	$UREGSPACE, R1

	BL	saveureg(SB)		/* addressed relative to PC */
	BL	trap(SB)
	BR	restoreureg

/*
 * enter with stack set and mapped.
 * on return, SB (R2) has been set, and R3 has the Ureg*,
 * the MMU has been re-enabled, kernel text and PC are in KSEG,
 * R(MACH) has been set, and R0 contains 0.
 *
 */
TEXT saveureg(SB), $-4
/*
 * save state
 */
	MOVMW	R2, 48(R1)		/* save r2 .. r31 in 48(R1) .. 164(R1) */
	MOVW	$MACHPADDR, R(MACH)	/* PADDR(m->) */
	MOVW	8(R(MACH)), R(USER)	/* up-> */
	MOVW	$MACHADDR, R(MACH)	/* m-> */
	MOVW	SPR(SAVER1), R4
	MOVW	R4, 44(R1)
	MOVW	SPR(SAVER0), R5
	MOVW	R5, 40(R1)
	MOVW	CTR, R6
	MOVW	R6, 36(R1)
	MOVW	XER, R4
	MOVW	R4, 32(R1)
	MOVW	CR, R5
	MOVW	R5, 28(R1)
	MOVW	SPR(SAVELR), R6		/* LR */
	MOVW	R6, 24(R1)
	/* pad at 20(R1) */
	MOVW	SPR(SRR0), R0
	MOVW	R0, 16(R1)		/* old PC */
	MOVW	SPR(SRR1), R0
	MOVW	R0, 12(R1)		/* old status */
	MOVW	SPR(SAVEXX), R0
	MOVW	R0, 8(R1)		/* cause/vector */
	MOVW	SPR(DCMP), R0
	MOVW	R0, (160+8)(R1)
	MOVW	SPR(iCMP), R0
	MOVW	R0, (164+8)(R1)
	MOVW	SPR(DMISS), R0
	MOVW	R0, (168+8)(R1)
	MOVW	SPR(IMISS), R0
	MOVW	R0, (172+8)(R1)
	MOVW	SPR(HASH1), R0
	MOVW	R0, (176+8)(R1)
	MOVW	SPR(HASH2), R0
	MOVW	R0, (180+8)(R1)
	MOVW	SPR(DAR), R0
	MOVW	R0, (184+8)(R1)
	MOVW	SPR(DSISR), R0
	MOVW	R0, (188+8)(R1)
	ADD	$8, R1, R3		/* Ureg* */
	OR	$KZERO, R3		/* fix ureg */
	STWCCC	R3, (R1)		/* break any pending reservations */
	MOVW	$0, R0			/* compiler/linker expect R0 to be zero */
	MOVW	$setSB(SB), R2		/* SB register */

	MOVW	MSR, R5
	OR	$(MSR_IR|MSR_DR|MSR_FP|MSR_RI), R5	/* enable MMU */
	MOVW	R5, SPR(SRR1)
	MOVW	LR, R31
	OR	$KZERO, R31		/* return PC in KSEG0 */
	MOVW	R31, SPR(SRR0)
	OR	$KZERO, R1		/* fix stack pointer */
	RFI				/* returns to trap handler */

/*
 * restore state from Ureg and return from trap/interrupt
 */
TEXT forkret(SB), $0
	BR	restoreureg

restoreureg:
	MOVMW	48(R1), R2		/* restore r2 through r31 */
	/* defer R1 */
	MOVW	40(R1), R0
	MOVW	R0, SPR(SAVER0)		/* resave saved R0 */
	MOVW	36(R1), R0
	MOVW	R0, CTR
	MOVW	32(R1), R0
	MOVW	R0, XER
	MOVW	28(R1), R0
	MOVW	R0, CR			/* Condition register*/
	MOVW	24(R1), R0
	MOVW	R0, LR
	/* pad, skip */
	MOVW	16(R1), R0
	MOVW	R0, SPR(SRR0)		/* old PC */
	MOVW	12(R1), R0
	MOVW	R0, SPR(SRR1)		/* old MSR */
	/* cause, skip */
	MOVW	44(R1), R1		/* old SP */
	MOVW	SPR(SAVER0), R0
	RFI

TEXT getpvr(SB), $0
	MOVW	SPR(PVR), R3
	RETURN

TEXT getdec(SB), $0
	MOVW	SPR(DEC), R3
	RETURN

TEXT putdec(SB), $0
	MOVW	R3, SPR(DEC)
	RETURN

TEXT getdar(SB), $0
	MOVW	SPR(DAR), R3
	RETURN

TEXT getdsisr(SB), $0
	MOVW	SPR(DSISR), R3
	RETURN

TEXT getmsr(SB), $0
	MOVW	MSR, R3
	RETURN

TEXT putmsr(SB), $0
	MOVW	R3, MSR
	MSRSYNC
	RETURN

TEXT putsdr1(SB), $0
	SYNC
	MOVW	R3, SPR(SDR1)
	ISYNC
	RETURN

TEXT putsr(SB), $0
	MOVW	4(FP), R4
	SYNC
	MOVW	R4, SEG(R3)
	MSRSYNC
	RETURN

TEXT getsr(SB), $0
	MOVW	SEG(R3), R3
	RETURN

TEXT gethid0(SB), $0
	MOVW	SPR(HID0), R3
	RETURN

TEXT puthid0(SB), $0
	SYNC
	ISYNC
	MOVW	R3, SPR(HID0)
	SYNC
	RETURN

TEXT gethid1(SB), $0
	MOVW	SPR(HID1), R3
	RETURN

TEXT gethid2(SB), $0
	MOVW	SPR(HID2), R3
	RETURN

TEXT puthid2(SB), $0
	MOVW	R3, SPR(HID2)
	RETURN

TEXT eieio(SB), $0
	EIEIO
	RETURN

TEXT sync(SB), $0
	SYNC
	RETURN

/* Power PC 603e specials */
TEXT getimiss(SB), $0
	MOVW	SPR(IMISS), R3
	RETURN

TEXT geticmp(SB), $0
	MOVW	SPR(iCMP), R3
	RETURN

TEXT puticmp(SB), $0
	MOVW	R3, SPR(iCMP)
	RETURN

TEXT getdmiss(SB), $0
	MOVW	SPR(DMISS), R3
	RETURN

TEXT getdcmp(SB), $0
	MOVW	SPR(DCMP), R3
	RETURN

TEXT putdcmp(SB), $0
	MOVW	R3, SPR(DCMP)
	RETURN

TEXT getsdr1(SB), $0
	MOVW	SPR(SDR1), R3
	RETURN

TEXT gethash1(SB), $0
	MOVW	SPR(HASH1), R3
	RETURN

TEXT puthash1(SB), $0
	MOVW	R3, SPR(HASH1)
	RETURN

TEXT gethash2(SB), $0
	MOVW	SPR(HASH2), R3
	RETURN

TEXT puthash2(SB), $0
	MOVW	R3, SPR(HASH2)
	RETURN

TEXT getrpa(SB), $0
	MOVW	SPR(RPA), R3
	RETURN

TEXT putrpa(SB), $0
	MOVW	R3, SPR(RPA)
	RETURN

TEXT tlbli(SB), $0
	TLBLI(3)
	ISYNC
	RETURN

TEXT tlbld(SB), $0
	SYNC
	TLBLD(3)
	ISYNC
	RETURN

TEXT getsrr1(SB), $0
	MOVW	SPR(SRR1), R3
	RETURN

TEXT putsrr1(SB), $0
	MOVW	R3, SPR(SRR1)
	RETURN

TEXT fpsave(SB), $0
	FMOVD	F0, (0*8)(R3)
	FMOVD	F1, (1*8)(R3)
	FMOVD	F2, (2*8)(R3)
	FMOVD	F3, (3*8)(R3)
	FMOVD	F4, (4*8)(R3)
	FMOVD	F5, (5*8)(R3)
	FMOVD	F6, (6*8)(R3)
	FMOVD	F7, (7*8)(R3)
	FMOVD	F8, (8*8)(R3)
	FMOVD	F9, (9*8)(R3)
	FMOVD	F10, (10*8)(R3)
	FMOVD	F11, (11*8)(R3)
	FMOVD	F12, (12*8)(R3)
	FMOVD	F13, (13*8)(R3)
	FMOVD	F14, (14*8)(R3)
	FMOVD	F15, (15*8)(R3)
	FMOVD	F16, (16*8)(R3)
	FMOVD	F17, (17*8)(R3)
	FMOVD	F18, (18*8)(R3)
	FMOVD	F19, (19*8)(R3)
	FMOVD	F20, (20*8)(R3)
	FMOVD	F21, (21*8)(R3)
	FMOVD	F22, (22*8)(R3)
	FMOVD	F23, (23*8)(R3)
	FMOVD	F24, (24*8)(R3)
	FMOVD	F25, (25*8)(R3)
	FMOVD	F26, (26*8)(R3)
	FMOVD	F27, (27*8)(R3)
	FMOVD	F28, (28*8)(R3)
	FMOVD	F29, (29*8)(R3)
	FMOVD	F30, (30*8)(R3)
	FMOVD	F31, (31*8)(R3)
	MOVFL	FPSCR, F0
	FMOVD	F0, (32*8)(R3)
	RETURN

TEXT fprestore(SB), $0
	FMOVD	(32*8)(R3), F0
	MOVFL	F0, FPSCR
	FMOVD	(0*8)(R3), F0
	FMOVD	(1*8)(R3), F1
	FMOVD	(2*8)(R3), F2
	FMOVD	(3*8)(R3), F3
	FMOVD	(4*8)(R3), F4
	FMOVD	(5*8)(R3), F5
	FMOVD	(6*8)(R3), F6
	FMOVD	(7*8)(R3), F7
	FMOVD	(8*8)(R3), F8
	FMOVD	(9*8)(R3), F9
	FMOVD	(10*8)(R3), F10
	FMOVD	(11*8)(R3), F11
	FMOVD	(12*8)(R3), F12
	FMOVD	(13*8)(R3), F13
	FMOVD	(14*8)(R3), F14
	FMOVD	(15*8)(R3), F15
	FMOVD	(16*8)(R3), F16
	FMOVD	(17*8)(R3), F17
	FMOVD	(18*8)(R3), F18
	FMOVD	(19*8)(R3), F19
	FMOVD	(20*8)(R3), F20
	FMOVD	(21*8)(R3), F21
	FMOVD	(22*8)(R3), F22
	FMOVD	(23*8)(R3), F23
	FMOVD	(24*8)(R3), F24
	FMOVD	(25*8)(R3), F25
	FMOVD	(26*8)(R3), F26
	FMOVD	(27*8)(R3), F27
	FMOVD	(28*8)(R3), F28
	FMOVD	(29*8)(R3), F29
	FMOVD	(30*8)(R3), F30
	FMOVD	(31*8)(R3), F31
	RETURN

TEXT dcacheenb(SB), $0
	SYNC
	MOVW	SPR(HID0), R4		/* Get HID0 and clear unwanted bits */
	RLWNM	$0, R4, $~(HID_DLOCK), R4
	MOVW	$(HID_DCFI|HID_DCE), R5
	OR	R4, R5
	MOVW	$HID_DCE, R3
	OR	R4, R3
	SYNC
//	MOVW	R5, SPR(HID0)		/* Cache enable and flash invalidate */
	MOVW	R3, SPR(HID0)		/* Cache enable */
	SYNC
	RETURN

TEXT icacheenb(SB), $0
	SYNC
	MOVW	SPR(HID0), R4		/* Get HID0 and clear unwanted bits */
	RLWNM	$0, R4, $~(HID_ILOCK), R4
	MOVW	$(HID_ICFI|HID_ICE), R5
	OR	R4, R5
	MOVW	$HID_ICE, R3
	OR	R4, R3
	SYNC
	MOVW	R5, SPR(HID0)		/* Cache enable and flash invalidate */
	MOVW	R3, SPR(HID0)		/* Cache enable */
	SYNC
	RETURN

#ifdef ucuconf
TEXT getpll(SB), $0
	MOVW	SPR(1009), R3
	ISYNC
	RETURN

TEXT getl2pm(SB), $0
	MOVW	SPR(1016), R3
	RETURN

TEXT getl2cr(SB), $0
	MOVW	SPR(1017), R3
	RETURN

TEXT putl2cr(SB), $0
	MOVW	R3, SPR(1017)
	RETURN

TEXT dcachedis(SB), $0
	SYNC
/*	MOVW	SPR(HID0), R4
	RLWNM	$0, R4, $~(HID_DCE), R4
	MOVW	R4, SPR(HID0)		/* L1 Cache disable */

	MOVW	SPR(1017), R4
	RLWNM	$0, R4, $~(0x80000000), R4
	MOVW	R4, SPR(1017)		/* L2 Cache disable */

	SYNC
	RETURN

TEXT l2disable(SB), $0
	SYNC
	MOVW	SPR(1017), R4
	RLWNM	$0, R4, $~(0x80000000), R4
	MOVW	R4, SPR(1017)		/* L2 Cache disable */
	SYNC
	RETURN

TEXT getbats(SB), $0
	MOVW	SPR(DBATU(0)), R4
	MOVW	R4, 0(R3)
	MOVW	SPR(DBATL(0)), R4
	MOVW	R4, 4(R3)
	MOVW	SPR(IBATU(0)), R4
	MOVW	R4, 8(R3)
	MOVW	SPR(IBATL(0)), R4
	MOVW	R4, 12(R3)
	MOVW	SPR(DBATU(1)), R4
	MOVW	R4, 16(R3)
	MOVW	SPR(DBATL(1)), R4
	MOVW	R4, 20(R3)
	MOVW	SPR(IBATU(1)), R4
	MOVW	R4, 24(R3)
	MOVW	SPR(IBATL(1)), R4
	MOVW	R4, 28(R3)
	MOVW	SPR(DBATU(2)), R4
	MOVW	R4, 32(R3)
	MOVW	SPR(DBATL(2)), R4
	MOVW	R4, 36(R3)
	MOVW	SPR(IBATU(2)), R4
	MOVW	R4, 40(R3)
	MOVW	SPR(IBATL(2)), R4
	MOVW	R4, 44(R3)
	MOVW	SPR(DBATU(3)), R4
	MOVW	R4, 48(R3)
	MOVW	SPR(DBATL(3)), R4
	MOVW	R4, 52(R3)
	MOVW	SPR(IBATU(3)), R4
	MOVW	R4, 56(R3)
	MOVW	SPR(IBATL(3)), R4
	MOVW	R4, 60(R3)
	RETURN

TEXT setdbat0(SB), $0
	MOVW	0(R3), R4
	MOVW	R4, SPR(DBATU(0))
	MOVW	4(R3), R4
	MOVW	R4, SPR(DBATL(0))
	RETURN
#endif /* ucuconf */

TEXT mmudisable(SB), $0
	/* disable MMU */
	MOVW	LR, R4
	MOVW	$KZERO, R5
	ANDN	R5, R4
	MOVW	R4, SPR(SRR0)		/* Stored PC for RFI instruction */

	MOVW	MSR, R4
	MOVW	$(MSR_IR|MSR_DR|MSR_RI|MSR_FP), R5
	ANDN	R5, R4
	MOVW	R4, SPR(SRR1)

	MOVW	SPR(HID0), R4		/* Get HID0 and clear unwanted bits */
	MOVW	$(HID_ICE|HID_DCE), R5
	ANDN	R5, R4
	MOVW	R4, SPR(HID0)		/* Cache disable */
	RFI				/* resume caller with MMU off */
	RETURN

TEXT kreboot(SB), $0
	BL	mmudisable(SB)
	MOVW	R3, LR
	RETURN

TEXT mul64fract(SB), $0
	MOVW	a0+8(FP), R9
	MOVW	a1+4(FP), R10
	MOVW	b0+16(FP), R4
	MOVW	b1+12(FP), R5

	MULLW	R10, R5, R13		/* c2 = lo(a1*b1) */

	MULLW	R10, R4, R12		/* c1 = lo(a1*b0) */
	MULHWU	R10, R4, R7		/* hi(a1*b0) */
	ADD	R7, R13			/* c2 += hi(a1*b0) */

	MULLW	R9, R5, R6		/* lo(a0*b1) */
	MULHWU	R9, R5, R7		/* hi(a0*b1) */
	ADDC	R6, R12			/* c1 += lo(a0*b1) */
	ADDE	R7, R13			/* c2 += hi(a0*b1) + carry */

	MULHWU	R9, R4, R7		/* hi(a0*b0) */
	ADDC	R7, R12			/* c1 += hi(a0*b0) */
	ADDE	R0, R13			/* c2 += carry */

	MOVW	R12, 4(R3)
	MOVW	R13, 0(R3)
	RETURN