m8260.h

这是一个同样来自贝尔实验室的和UNIX有着渊源的操作系统, 其简洁的设计和实现易于我们学习和理解

/*0x10C1C*/	ulong	simr_h;		/*  SIU interrupt mask register(high) 32 bits 4.3.1.5/4-22 */
/*0x10C20*/	ulong	simr_l;		/*  SIU interrupt mask register(low) 32 bits 4.3.1.5/4-22 */
/*0x10C24*/	ulong	siexr;		/*  SIUexternal interrupt control register 32 bits 4.3.1.7/4-24 */
/*0x10C28*/	uchar	Rsvd10C28[88];

/* Clocksand Reset */
/*0x10C80*/	ulong	sccr;			/*  Systemclock control register 32 bits 9.8/9-8 */
/*0x10C84*/	uchar	Rsvd10C84[4];
/*0x10C88*/	ulong	scmr;		/*  Systemclock mode register 32 bits 9.9/9-9 */
/*0x10C8C*/	uchar	Rsvd10C8C[4];
/*0x10C90*/	ulong	rsr;			/*  Reset status register 32 bits 5.2/5-4 */
/*0x10C94*/	ulong	rmr;			/*  Reset mode register 32 bits 5.3/5-5 */
/*0x10C98*/	uchar	Rsvd10C98[104];

/* Part I.Overview Input/Output Port */
/*0x10D00*/	Port		port[4];

/* CPMTimers */
/*0x10D80*/	uchar	tgcr1;		/*  Timer1 and timer2 global configuration register 8 bits 17.2.2/17-4 */

/*0x10D81*/	uchar	Rsvd10D81[3];
/*0x10D84*/	uchar	tgcr2;		/*  Timer3 and timer4 global configuration register 8 bits 17.2.2/17-4 */
/*0x10D85*/	uchar	Rsvd10D85[3];

/*0x10D88*/	uchar	Rsvd10D88[8];
/*0x10D90*/	ushort	tmr1;		/*  Timer1 mode register 16 bits 17.2.3/17-6 */
/*0x10D92*/	ushort	tmr2;		/*  Timer2 mode register 16 bits 17.2.3/17-6 */
		union{
			struct {
/*0x10D94*/	ushort	trr1;			/*  Timer1 reference register 16 bits 17.2.4/17-7 */
/*0x10D96*/	ushort	trr2;			/*  Timer2 reference register 16 bits 17.2.4/17-7 */
			};
/*0x10D94*/	ulong	trrl1;			/*  Combined Timer 1/2 trr register */
		};
		union{
			struct {
/*0x10D98*/	ushort	tcr1;			/*  Timer1 capture register 16 bits 17.2.5/17-8 */
/*0x10D9A*/	ushort	tcr2;			/*  Timer2 capture register 16 bits 17.2.5/17-8 */
			};
/*0x10D98*/	ulong	tcrl1;		/*  Combined timer1/2 capture register */
		};
		union{
			struct {
/*0x10D9C*/	ushort	tcn1;			/*  Timer1 counter 16 bits 17.2.6/17-8 */
/*0x10D9E*/	ushort	tcn2;			/*  Timer2 counter 16 bits 17.2.6/17-8 */
			};
/*0x10D9C*/	ulong	tcnl1;		/*  Combined timer1/2 counter */
		};
/*0x10DA0*/	ushort	tmr3;		/*  Timer3 mode register 16 bits 17.2.3/17-6 */
/*0x10DA2*/	ushort	tmr4;		/*  Timer4 mode register 16 bits 17.2.3/17-6 */
		union{
			struct {
/*0x10DA4*/	ushort	trr3;			/*  Timer3 reference register 16 bits 17.2.4/17-7 */
/*0x10DA6*/	ushort	trr4;			/*  Timer4 reference register 16 bits 17.2.4/17-7 */
			};
/*0x10DA4*/	ulong	trrl3;
		};			
		union{
			struct {
/*0x10DA8*/	ushort	tcr3;			/*  Timer3 capture register 16 bits 17.2.5/17-8 */
/*0x10DAA*/	ushort	tcr4;			/*  Timer4 capture register 16 bits 17.2.5/17-8 */
			};
/*0x10DA8*/	ulong	tcrl3;
		};
		union{
			struct {
/*0x10DAC*/	ushort	tcn3;			/*  Timer3 counter 16 bits 17.2.6/17-8 */
/*0x10DAE*/	ushort	tcn4;			/*  Timer4 counter 16 bits 17.2.6/17-8 */
			};
/*0x10DAC*/	ulong	tcnl3;
		};
/*0x10DB0*/	ushort	ter1;			/*  Timer1 event register 16 bits 17.2.7/17-8 */
/*0x10DB2*/	ushort	ter2;			/*  Timer2 event register 16 bits 17.2.7/17-8 */
/*0x10DB4*/	ushort	ter3;			/*  Timer3 event register 16 bits 17.2.7/17-8 */
/*0x10DB6*/	ushort	ter4;			/*  Timer4 event register 16 bits 17.2.7/17-8 */
/*0x10DB8*/	uchar	Rsvd10DB8[608];

/* SDMADHGeneral */
/*0x11018*/	uchar	sdsr;			/*  SDMA status register 8 bits 18.2.1/18-3 */
/*0x11019*/	uchar	Rsvd11019[3];
/*0x1101C*/	uchar	sdmr;		/*  SDMA mask register 8 bits 18.2.2/18-4 */
/*0x1101D*/	uchar	Rsvd1101D[3];

/* IDMA */
/*0x11020*/	IDMA	idma[4];

/*0x11040*/	uchar	Rsvd11040[704];

/*0x11300*/	FCC		fcc[3];

/*0x11360*/	uchar	Rsvd11360[0x290];

/* BRGs5DH8 */
/*0x115F0*/	ulong	BRGC5;		/*  BRG5 configuration register 32 bits 16.1/16-2 */
/*0x115F4*/	ulong	BRGC6;		/*  BRG6configuration register 32 bits */
/*0x115F8*/	ulong	BRGC7;		/*  BRG7configuration register 32 bits */
/*0x115FC*/	ulong	BRGC8;		/*  BRG8configuration register 32 bits */
/*0x11600*/	uchar	Rsvd11600[0x260];
/*0x11860*/	uchar	I2MOD;		/*  I2C mode register 8 bits 34.4.1/34-6 */
/*0x11861*/	uchar	Rsvd11861[3];
/*0x11864*/	uchar	I2ADD;		/*  I2C address register 8 bits 34.4.2/34-7 */
/*0x11865*/	uchar	Rsvd11865[3];
/*0x11868*/	uchar	I2BRG;		/*  I2C BRG register 8 bits 34.4.3/34-7 */
/*0x11869*/	uchar	Rsvd11869[3];
/*0x1186C*/	uchar	I2COM;		/*  I2C command register 8 bits 34.4.5/34-8 */
/*0x1186D*/	uchar	Rsvd1186D[3];
/*0x11870*/	uchar	I2CER;		/*  I2C event register 8 bits 34.4.4/34-8 */
/*0x11871*/	uchar	Rsvd11871[3];
/*0x11874*/	uchar	I2CMR;		/*  I2C mask register 8 bits 34.4.4/34-8 */
/*0x11875*/	uchar	Rsvd11875[331];

/* Communications Processor */
/*0x119C0*/	ulong	cpcr;		/*  Communications processor command register 32 bits 13.4.1/13-11 */

/*0x119C4*/	ulong	rccr;		/*  CP configuration register 32 bits 13.3.6/13-7 */
/*0x119C8*/	uchar	Rsvd119C8[14];
/*0x119D6*/	ushort	rter;		/*  CP timers event register 16 bits 13.6.4/13-21 */
/*0x119D8*/	ushort	Rsvd119D8;
/*0x119DA*/	ushort	rtmr;		/*  CP timers mask register 16 bits */
/*0x119DC*/	ushort	rtscr;		/*  CPtime-stamp timer control register 16 bits 13.3.7/13-9 */
/*0x119DE*/	ushort	Rsvd119DE;
/*0x119E0*/	ulong	rtsr;		/*  CPtime-stamp register 32 bits 13.3.8/13-10 */
/*0x119E4*/	uchar	Rsvd119E4[12];

/*0x119F0*/	ulong	brgc[4];		/*  BRG configuration registers 32 bits 16.1/16-2 */

/*0x11A00*/	SCC		scc[4];

/*0x11A80*/	SMC		smc[2];

			SPI		spi;

/*0x11AB0*/	uchar	Rsvd11AB0[80];

/* CPMMux */
/*0x11B00*/	uchar	cmxsi1cr;	/*  CPM mux SI1clock route register 8 bits 15.4.2/15-10 */
/*0x11B01*/	uchar	Rsvd11B01;
/*0x11B02*/	uchar	cmxsi2cr;	/*  CPM mux SI2clock route register 8 bits 15.4.3/15-11 */
/*0x11B03*/	uchar	Rsvd11B03;
/*0x11B04*/	ulong	cmxfcr;	/*  CPM mux FCC clock route register 32 bits 15.4.4/15-12 */
/*0x11B08*/	ulong	cmxscr;	/*  CPM mux SCC clock route register 32 bits 15.4.5/15-14 */
/*0x11B0C*/	uchar	cmxsmr;	/*  CPM mux SMC clock route register 8 bits 15.4.6/15-17 */
/*0x11B0D*/	uchar	Rsvd11B0D;
/*0x11B0E*/	ushort	cmxuar;	/*  CPM mux UTOPIA address register 16 bits 15.4.1/15-7 */
/*0x11B10*/	uchar	Rsvd11B10[16];

			SI		si1;			/* SI 1 Registers */

/* MCC1Registers */
/*0x11B30*/	ushort	MCCE1;		/*  MCC1 event register 16 bits 27.10.1/27-18 */
/*0x11B32*/	ushort	Rsvd11B32;
/*0x11B34*/	ushort	MCCM1;		/*  MCC1 mask register 16 bits */
/*0x11B36*/	ushort	Rsvd11B36;
/*0x11B38*/	uchar	MCCF1;		/*  MCC1 configuration register 8 bits 27.8/27-15 */
/*0x11B39*/	uchar	Rsvd11B39[7];

			SI		si2;			/* SI 2 Registers */

/* MCC2Registers */
/*0x11B50*/	ushort	MCCE2;		/*  MCC2 event register 16 bits 27.10.1/27-18 */
/*0x11B52*/	ushort	Rsvd11B52;
/*0x11B54*/	ushort	MCCM2;		/*  MCC2 mask register 16 bits */
/*0x11B56*/	ushort	Rsvd11B56;
/*0x11B58*/	uchar	MCCF2;		/*  MCC2 configuration register 8 bits 27.8/27-15 */
/*0x11B59*/	uchar	Rsvd11B59[1191];

/* SI1RAM */
/*0x12000*/	uchar	SI1TxRAM[0x200];/*  SI1 transmit routing RAM	512 14.4.3/14-10 */
/*0x12200*/	uchar	Rsvd12200[0x200];
/*0x12400*/	uchar	SI1RxRAM[0x200];/*  SI1 receive routing RAM	512 14.4.3/14-10 */
/*0x12600*/	uchar	Rsvd12600[0x200];

/* SI2RAM */
/*0x12800*/	uchar	SI2TxRAM[0x200];/*  SI2 transmit routing RAM	512 14.4.3/14-10 */
/*0x12A00*/	uchar	Rsvd12A00[0x200];
/*0x12C00*/	uchar	SI2RxRAM[0x200];/*  SI2 receive routing RAM	512 14.4.3/14-10 */
/*0x12E00*/	uchar	Rsvd12E00[0x200];
/*0x13000*/	uchar	Rsvd13000[0x800];
/*0x13800*/	uchar	Rsvd13800[0x800];
};

typedef struct FCCextra FCCextra;
struct FCCextra {
/*0x00*/	uchar	ri[0x20];
/*0x20*/	uchar	ti[0x20];
/*0x40*/	uchar	pad[0x20];
};

typedef struct Imap Imap;
struct Imap {
/* CPMDual-Port RAM */
/*0x00000*/	uchar	dpram1[0x3800];	/*  Dual-port RAM	16Kbytes 13.5/13-15 */
/*0x03800*/	FCCextra	fccextra[4];
/*0x03980*/	Uartsmc	uartsmc[2];
/*0x03a00*/	uchar	dsp1p[0x40];
/*0x03a40*/	uchar	dsp2p[0x40];
/*0x03a80*/	BD		bd[(0x04000-0x03a80)/sizeof(BD)];	/* Buffer descriptors */
/*0x04000*/	uchar	Rsvd4000[0x04000];

/* Dual port RAM bank 2 -- Parameter Ram, Section 13.5 */
/*0x08000*/	PrmSCC	prmscc[4];
/*0x08400*/	PrmFCC	prmfcc[3];
/*0x08700*/	Bases	param[4];
/*0x08b00*/	uchar	dpram2[0x500];

/*0x09000*/	uchar	Rsvd9000[0x2000];

/* Dual port RAM bank 3 -- Section 13.5 */
/*0x0B000*/	uchar	dpram3[0x1000];	/*  Dual-port RAM	4Kbytes 13.5/13-15 */
/*0x0C000*/	uchar	Rsvdc000[0x4000];

/*0x10000*/	IMM;
};

enum {
/* CPM Command register. */
	cpm_rst		= 0x80000000,
	cpm_page	= 0x7c000000,
	cpm_sblock	= 0x03e00000,
	cpm_flg		= 0x00010000,
	cpm_mcn		= 0x00003fc0,
	cpm_opcode	= 0x0000000f,

/* Device sub-block and page codes. */
	cpm_fcc1_sblock	= 0x10,
	cpm_fcc2_sblock	= 0x11,
	cpm_fcc3_sblock	= 0x12,
	cpm_scc1_sblock	= 0x04,
	cpm_scc2_sblock	= 0x05,
	cpm_scc3_sblock	= 0x06,
	cpm_scc4_sblock	= 0x07,
	cpm_smc1_sblock	= 0x08,
	cpm_smc2_sblock	= 0x09,
	cpm_rand_sblock	= 0x0e,
	cpm_spi_sblock	= 0x0a,
	cpm_i2c_sblock	= 0x0b,
	cpm_timer_sblock	= 0x0f,
	cpm_mcc1_sblock	= 0x1c,
	cpm_mcc2_sblock	= 0x1d,
	cpm_idma1_sblock	= 0x14,
	cpm_idma2_sblock	= 0x15,
	cpm_idma3_sblock	= 0x16,
	cpm_idma4_sblock	= 0x17,

	cpm_scc1_page	= 0x00,
	cpm_scc2_page	= 0x01,
	cpm_scc3_page	= 0x02,
	cpm_scc4_page	= 0x03,
	cpm_smc1_page	= 0x07,
	cpm_smc2_page	= 0x08,
	cpm_spi_page		= 0x09,
	cpm_i2c_page		= 0x0a,
	cpm_timer_page	= 0x0a,
	cpm_rand_page	= 0x0a,
	cpm_fcc1_page	= 0x04,
	cpm_fcc2_page	= 0x05,
	cpm_fcc3_page	= 0x06,
	cpm_idma1_page	= 0x07,
	cpm_idma2_page	= 0x08,
	cpm_idma3_page	= 0x09,
	cpm_idma4_page	= 0x0a,
	cpm_mcc1_page	= 0x07,
	cpm_mcc2_page	= 0x08,

};

/*
 * CPM
 */
enum {
	/* commands */
	InitRxTx =	0,
	InitRx =		1,
	InitTx =		2,
	EnterHunt=	3,
	StopTx=		4,
	GracefulStopTx = 5,
	InitIDMA =	5,
	RestartTx =	6,
	CloseRxBD =	7,
	SetGroupAddr = 8,
	SetTimer =	8,
	GCITimeout =	9,
	GCIAbort =	10,
	StopIDMA =	11,
	StartDSP = 	12,
	ArmIDMA =	13,
	InitDSP =		13,
	USBCmd =	15,

	/* channel IDs */
	SCC1ID=	cpm_scc1_page << 5 | cpm_scc1_sblock,
	SCC2ID=	cpm_scc2_page << 5 | cpm_scc2_sblock,
	SCC3ID=	cpm_scc3_page << 5 | cpm_scc3_sblock,
	SMC1ID=	cpm_smc1_page << 5 | cpm_smc1_sblock,
	SMC2ID=	cpm_smc2_page << 5 | cpm_smc2_sblock,
	FCC1ID=	cpm_fcc1_page << 5 | cpm_fcc1_sblock,
	FCC2ID=	cpm_fcc2_page << 5 | cpm_fcc2_sblock,
	FCC3ID=	cpm_fcc3_page << 5 | cpm_fcc3_sblock,
//	USBID=	0,		These are wrong
//	I2CID=	1,
//	IDMA1ID= 1,
//	SPIID=	5,
//	IDMA2ID= 5,
//	TIMERID=	5,
//	DSP1ID=9,
//	SCC4ID=	10,
//	DSP2ID=	13,

	/* sicr */
	BRG1 = 0,
	BRG2 = 1,
	BRG3 = 2,
	BRG4 = 4,
	CLK1 = 4,
	CLK2 = 5,
	CLK3 = 6,
	CLK4 = 7,

};

extern IMM* iomem;

BD*	bdalloc(int);
void	cpmop(int, int, int);
void	ioplock(void);
void	iopunlock(void);
void	kreboot(ulong);