m8260.h

这是一个同样来自贝尔实验室的和UNIX有着渊源的操作系统, 其简洁的设计和实现易于我们学习和理解

typedef struct BD BD;
struct BD {
	ushort	status;
	ushort	length;
	ulong	addr;
};

enum{
	BDEmpty=	SBIT(0),
	BDReady=	SBIT(0),
	BDWrap=		SBIT(2),
	BDInt=		SBIT(3),
	BDLast=		SBIT(4),
	BDFirst=	SBIT(5),
};

typedef struct Ring Ring;

struct Ring {
	BD*	rdr;		/* receive descriptor ring */
	void*	rrb;		/* receive ring buffers */
	int	rdrx;		/* index into rdr */
	int	nrdre;		/* length of rdr */

	BD*	tdr;		/* transmit descriptor ring */
	void**	txb;		/* corresponding transmit ring buffers */
	int	tdrh;		/* host index into tdr */
	int	tdri;		/* interface index into tdr */
	int	ntdre;		/* length of tdr */
	int	ntq;		/* pending transmit requests */
};

int	ioringinit(Ring*, int, int, int);

/*
 * MCC parameters
 */
typedef struct MCCparam MCCparam;
struct MCCparam {
/*0x00*/	ulong	mccbase;
/*0x04*/	ushort	mccstate;
/*0x06*/	ushort	mrblr;	
/*0x08*/	ushort	grfthr;	
/*0x0a*/	ushort	grfcnt;	
/*0x0c*/	ulong	rinttmp;
/*0x10*/	ulong	data0;
/*0x14*/	ulong	data1;
/*0x18*/	ulong	tintbase;
/*0x1c*/	ulong	tintptr;
/*0x20*/	ulong	tinttmp;
/*0x24*/	ushort	sctpbase;
/*0x26*/	ushort	Rsvd26;
/*0x28*/	ulong	cmask32;
/*0x2c*/	ushort	xtrabase;
/*0x2e*/	ushort	cmask16;
/*0x30*/	ulong	rinttmp[4];
/*0x40*/	struct {
			ulong	base;
			ulong	ptr;
		}		rint[4];
/*0x60*/	ulong	tstmp;
/*0x64*/
};
/*
 * IO controller parameters
 */
typedef struct IOCparam IOCparam;
struct IOCparam {
/*0x00*/	ushort	rbase;
/*0x02*/	ushort	tbase;
/*0x04*/	uchar	rfcr;
/*0x05*/	uchar	tfcr;
/*0x06*/	ushort	mrblr;
/*0x08*/	ulong	rstate;
/*0x0c*/	ulong	rxidp;
/*0x10*/	ushort	rbptr;
/*0x12*/	ushort	rxibc;
/*0x14*/	ulong	rxtemp;
/*0x18*/	ulong	tstate;
/*0x1c*/	ulong	txidp;
/*0x20*/	ushort	tbptr;
/*0x22*/	ushort	txibc;
/*0x24*/	ulong	txtemp;
/*0x28*/
};

typedef struct SCCparam SCCparam;
struct SCCparam {
	IOCparam;
	ulong	rcrc;
	ulong	tcrc;
};

typedef struct FCCparam FCCparam;
struct FCCparam {
/*0x00*/	ushort	riptr;
/*0x02*/	ushort	tiptr;
/*0x04*/	ushort	Rsvd04;
/*0x06*/	ushort	mrblr;
/*0x08*/	ulong	rstate;
/*0x0c*/	ulong	rbase;
/*0x10*/	ushort	rbdstat;
/*0x12*/	ushort	rbdlen;
/*0x14*/	char*	rdptr;
/*0x18*/	ulong	tstate;
/*0x1c*/	ulong	tbase;
/*0x20*/	ushort	tbdstat;
/*0x22*/	ushort	tbdlen;
/*0x24*/	ulong	tdptr;
/*0x28*/	ulong	rbptr;
/*0x2c*/	ulong	tbptr;
/*0x30*/	ulong	rcrc;
/*0x34*/	ulong	Rsvd34;
/*0x38*/	ulong	tcrc;
/*0x3c*/
};

typedef struct SCC SCC;
struct SCC {
	ulong	gsmrl;
	ulong	gsmrh;
	ushort	psmr;
	uchar	rsvscc0[2];
	ushort	todr;
	ushort	dsr;
	ushort	scce;
	uchar	rsvscc1[2];
	ushort	sccm;
	uchar	rsvscc2;
	uchar	sccs;
	ushort	irmode;
	ushort	irsip;
	uchar	rsvscc3[4];	/* BUG */
};

typedef struct FCC FCC;
struct FCC {
/*0x00*/	ulong	gfmr;		/*  general mode register 28.2/28-3 */
/*0x04*/	ulong	fpsmr;		/*  protocol-specific mode reg. 29.13.2(ATM) 30.18.1(Ether) */
/*0x08*/	ushort	ftodr;		/*  transmit on demand register 28.5/28-7 */
/*0x0A*/	ushort	Rsvd0A;
/*0x0C*/	ushort	fdsr;		/*  data synchronization register 28.4/28-7 */
/*0x0E*/	ushort	Rsvd0E;
/*0x10*/	ushort	fcce;		/* event register 29.13.3 (ATM), 30.18.2 (Ethernet) */
/*0x12*/	ushort	Rsvd12;
/*0x14*/	ushort	fccm;		/* mask register */
/*0x16*/	ushort	Rsvd16;
/*0x18*/	uchar	fccs;		/* status register 8 bits 31.10 (HDLC) */
/*0x19*/	uchar	Rsvd19[3];
/*0x1C*/	uchar	ftirrphy[4];	/* transmit internal rate registers for PHY0DH3 29.13.4/29-88 (ATM) */
/*0x20*/
};

typedef struct SMC SMC;
struct SMC {
/*0x0*/	ushort	pad1;
/*0x2*/	ushort	smcmr;
/*0x4*/	ushort	pad2;
/*0x6*/	uchar	smce;
/*0x7*/	uchar	pad3[3];
/*0xa*/	uchar	smcm;
/*0xb*/	uchar	pad4[5];
/*0x10*/
};

typedef struct SPI SPI;
struct SPI {
	ushort	spmode;
	uchar	res1[4];
	uchar	spie;
	uchar	res2[3];
	uchar	spim;
	uchar	res3[2];
	uchar	spcom;
	uchar	res4[2];
};

typedef struct Bankmap Bankmap;
struct Bankmap {
/*0*/	ulong	br;		/*  Base register bank 32 bits 10.3.1/10-14 */
/*4*/	ulong	or;		/*  Option register bank 32 bits 10.3.2/10-16 */
/*8*/
};

typedef struct Port Port;
struct Port {
/*0x00*/	ulong	pdir;		/*  Port A data direction register 32 bits 35.2.3/35-3 */
/*0x04*/	ulong	ppar;	/*  Port Apin assignment register 32 bits 35.2.4/35-4 */
/*0x08*/	ulong	psor;		/*  Port A special options register 32 bits 35.2.5/35-4 */
/*0x0C*/	ulong	podr;	/*  Port Aopen drain register 32 bits 35.2.1/35-2 */
/*0x10*/	ulong	pdat;		/*  Port A data register 32 bits 35.2.2/35-2 */
/*0x14*/	uchar	Rsvd14[12];
/*0x20*/
};

typedef struct IDMA IDMA;
struct IDMA {
/*0x0*/	uchar	idsr;		/*  IDMA event register 8 bits 18.8.4/18-22 */
/*0x1*/	uchar	Rsvd1[3];
/*0x4*/	uchar	idmr;	/*  IDMA mask register 8 bits 18.8.4/18-22 */
/*0x5*/	uchar	Rsvd5[3];
/*0x8*/
};

typedef struct PrmSCC PrmSCC;
struct PrmSCC {
	uchar	sccbytes[0x100];
};

typedef struct PrmFCC PrmFCC;
struct PrmFCC {
	uchar	fccbytes[0x100];
};

typedef struct Bases Bases;
struct Bases {
/*0x00*/	uchar	mcc[0x80];
/*0x80*/	uchar	Rsvd80[0x60];
/*0xe0*/	uchar	risctimers[0x10];
/*0xf0*/	ushort	revnum;
/*0xf2*/	uchar	Rsvdf2[6];
/*0xf8*/	ulong	rand;
/*0xfc*/	ushort	smcbase;
#define	i2cbase	smcbase
/*0xfe*/	ushort	idmabase;
/*0x100*/
};

typedef struct Uartsmc Uartsmc;
struct Uartsmc {
/*0x00*/	IOCparam;
/*0x28*/	ushort	maxidl;
/*0x2a*/	ushort	idlc;
/*0x2c*/	ushort	brkln;
/*0x2e*/	ushort	brkec;
/*0x30*/	ushort	brkcr;
/*0x32*/	ushort	r_mask;
/*0x34*/	ulong	sdminternal;
/*0x38*/	uchar	Rsvd38[8];
/*0x40*/
};

typedef struct SI SI;
struct SI {
/*0x11B20*/	ushort	siamr;		/*  SI TDMA1 mode register 16 bits 14.5.2/14-17 */
/*0x11B22*/	ushort	sibmr;		/*  SI TDMB1 mode register 16 bits */
/*0x11B24*/	ushort	sicmr;		/*  SI TDMC1 mode register 16 bits */
/*0x11B26*/	ushort	sidmr;		/*  SI TDMD1 mode register 16 bits */
/*0x11B28*/	uchar	sigmr;		/*  SI global mode register 8 bits 14.5.1/14-17 */
/*0x11B29*/	uchar	Rsvd11B29;
/*0x11B2A*/	ushort	sicmdr;		/*  SI command register 8 bits 14.5.4/14-24 */
/*0x11B2C*/	ushort	sistr;			/*  SI status register 8 bits 14.5.5/14-25 */
/*0x11B2E*/	ushort	sirsr;			/*  SI RAM shadow address register 16 bits 14.5.3/14-23 */
};

typedef struct IMM IMM;
struct IMM {
/* General SIU */
/*0x10000*/	ulong	siumcr;		/*  SIU module configuration register 32 bits 4.3.2.6/4-31 */
/*0x10004*/	ulong	sypcr;		/*  System protection control register 32 bits 4.3.2.8/4-35 */
/*0x10008*/	uchar	Rsvd10008[0xe-0x8];
/*0x1000E*/	ushort	swsr;		/*  Softwareservice register 16 bits 4.3.2.9/4-36 */
/*0x10010*/	uchar	Rsvd10010[0x14];
/*0x10024*/	ulong	bcr;			/*  Bus configuration register 32 bits 4.3.2.1/4-25 */
/*0x10028*/	ulong	PPC_ACR;		/*  60x bus arbiter configuration register 8 bits 4.3.2.2/4-28 */
/*0x1002C*/	ulong	PPCALRH;		/*  60x bus arbitration-level register high (first 8 clients) 32 bits 4.3.2.3/4-28 */
/*0x10030*/	ulong	PPC_ALRL;	/*  60x bus arbitration-level register low (next 8 clients) 32 bits 4.3.2.3/4-28 */
/*0x10034*/	ulong	LCL_ACR;		/*  Local arbiter configuration register 8 bits 4.3.2.4/4-29 */
/*0x10038*/	ulong	LCL_ALRH;	/*  Local arbitration-level register (first 8 clients) 32 bits 4.3.2.5/4-30 */

/*0x1003C*/	ulong	LCL_ALRL;	/*  Local arbitration-level register (next 8 clients) 32 bits 4.3.2.3/4-28 */
/*0x10040*/	ulong	TESCR1;		/*  60x bus transfer error status control register1 32 bits 4.3.2.10/4-36 */
/*0x10044*/	ulong	TESCR2;		/*  60x bus transfer error status control register2 32 bits 4.3.2.11/4-37 */
/*0x10048*/	ulong	L_TESCR1;	/*  Local bus transfer error status control register1 32 bits 4.3.2.12/4-38 */
/*0x1004C*/	ulong	L_TESCR2;	/*  Local bus transfer error status control register2 32 bits 4.3.2.13/4-39 */
/*0x10050*/	ulong	pdtea;		/*  60x bus DMAtransfer error address 32 bits 18.2.3/18-4 */
/*0x10054*/	uchar	pdtem;		/*  60x bus DMAtransfer error MSNUM 8 bits 18.2.4/18-4 */
/*0x10055*/	uchar	Rsvd10055[3];
/*0x10058*/	void*	ldtea;		/*  Local bus DMA transfer error address 32 bits 18.2.3/18-4 */
/*0x1005C*/	uchar	ldtem;		/*  Local bus DMA transfer error MSNUM 8 bits 18.2.4/18-4 */
/*0x1005D*/	uchar	Rsvd1005D[163];

/* Memory Controller */
/*0x10100*/	Bankmap	bank[12];

/*0x10160*/	uchar	Rsvd10160[8];
/*0x10168*/	void*	MAR;		/*  Memory address register 32 bits 10.3.7/10-29 */
/*0x1016C*/	ulong	Rsvd1016C;
/*0x10170*/	ulong	MAMR;		/*  Machine A mode register 32 bits 10.3.5/10-26 */
/*0x10174*/	ulong	MBMR;		/*  Machine B mode register 32 bits */
/*0x10178*/	ulong	MCMR;		/*  Machine C mode register 32 bits */
/*0x1017C*/	uchar	Rsvd1017C[6];
/*0x10184*/	ulong	mptpr;		/*  Memory periodic timer prescaler 16 bits 10.3.12/10-32 */
/*0x10188*/	ulong	mdr;			/*  Memorydata register 32 bits 10.3.6/10-28 */
/*0x1018C*/	ulong	Rsvd1018C;
/*0x10190*/	ulong	psdmr;		/*  60x bus SDRAM mode register 32 bits 10.3.3/10-21 */
/*0x10194*/	ulong	lsdmr;		/*  Local bus SDRAM mode register 32 bits 10.3.4/10-24 */
/*0x10198*/	ulong	PURT;		/*  60x bus-assigned UPM refresh timer 8 bits 10.3.8/10-30 */
/*0x1019C*/	ulong	PSRT;		/*  60x bus-assigned SDRAM refresh timer 8 bits 10.3.10/10-31 */

/*0x101A0*/	ulong	LURT;		/*  Local bus-assigned UPM refresh timer8 bits 10.3.9/10-30 */
/*0x101A4*/	ulong	LSRT;		/*  Local bus-assigned SDRAM refresh timer 8 bits 10.3.11/10-32 */

/*0x101A8*/	ulong	immr;		/*  Internal memory map register 32 bits 4.3.2.7/4-34 */
/*0x101AC*/	uchar	Rsvd101AC[84];
/* System Integration Timers */
/*0x10200*/	uchar	Rsvd10200[32];
/*0x10220*/	ulong	TMCNTSC;	/*  Time counter statusand control register 16 bits 4.3.2.14/4-40 */

/*0x10224*/	ulong	TMCNT;		/*  Time counter register 32 bits 4.3.2.15/4-41 */
/*0x10228*/	ulong	Rsvd10228;
/*0x1022C*/	ulong	TMCNTAL;	/*  Time counter alarm register 32 bits 4.3.2.16/4-41 */
/*0x10230*/	uchar	Rsvd10230[0x10];
/*0x10240*/	ulong	PISCR;		/*  Periodic interrupt statusand control register 16 bits 4.3.3.1/4-42 */

/*0x10244*/	ulong	PITC;		/*  Periodic interrupt count register 32 bits 4.3.3.2/4-43 */
/*0x10248*/	ulong	PITR;			/*  Periodic interrupt timer register 32 bits 4.3.3.3/4-44 */
/*0x1024C*/	uchar	Rsvd1024C[94];
/*0x102AA*/	uchar	Rsvd102AA[2390];

/* Interrupt Controller */
/*0x10C00*/	ushort	sicr;			/*  SIU interrupt configuration register 16 bits 4.3.1.1/4-17 */
/*0x10C02*/	ushort	Rsvd10C02;
/*0x10C04*/	ulong	sivec;		/*  SIU interrupt vector register 32 bits 4.3.1.6/4-23 */
/*0x10C08*/	ulong	sipnr_h;		/*  SIU interrupt pending register(high) 32 bits 4.3.1.4/4-21 */
/*0x10C0C*/	ulong	sipnr_l;		/*  SIU interrupt pending register(low) 32 bits 4.3.1.4/4-21 */
/*0x10C10*/	ulong	siprr;		/*  SIU interrupt priority register 32 bits 4.3.1.2/4-18 */
/*0x10C14*/	ulong	scprr_h;		/*  CPM interrupt priority register(high) 32 bits 4.3.1.3/4-19 */
/*0x10C18*/	ulong	scprr_l;		/*  CPM interrupt priority register(low) 32 bits 4.3.1.3/4-19 */