l.s

这是一个同样来自贝尔实验室的和UNIX有着渊源的操作系统, 其简洁的设计和实现易于我们学习和理解

TEXT cpsrr(SB), $-4
	MOVW	CPSR, R0
	RET

TEXT spsrr(SB), $-4
	MOVW	SPSR, R0
	RET

TEXT getsp(SB), $-4
	MOVW	R13, R0
	RET

TEXT getlink(SB), $-4
	MOVW	R14, R0
	RET

TEXT getcallerpc(SB), $-4
	MOVW	0(R13), R0
	RET

TEXT tas(SB), $-4
	MOVW	R0, R1
	MOVW	$0xDEADDEAD, R0
	MOVW	R0, R3
	SWPW	R0, (R1)
	CMP.S	R0, R3
	BEQ	_tasout
	EOR	R3, R3
	CMP.S	R0, R3
	BEQ	_tasout
	MOVW	$1,R15
_tasout:
	RET

TEXT setlabel(SB), $-4
	MOVW	R13, 0(R0)			/* sp */
	MOVW	R14, 4(R0)			/* pc */
	MOVW	$0, R0
	RET

TEXT gotolabel(SB), $-4
	MOVW	0(R0), R13			/* sp */
	MOVW	4(R0), R14			/* pc */
	MOVW	$1, R0
	RET

/* save the state machine in power_state[] for an upcoming suspend
 */
TEXT setpowerlabel(SB), $-4
	MOVW	$power_state+0(SB), R0
	/* svc */				/* power_state[]: what */
	MOVW	R1, 0(R0)
	MOVW	R2, 4(R0)
	MOVW	R3, 8(R0)
	MOVW	R4, 12(R0)
	MOVW	R5, 16(R0)
	MOVW	R6, 20(R0)
	MOVW	R7, 24(R0)
	MOVW	R8, 28(R0)
	MOVW	R9, 32(R0)
	MOVW	R10,36(R0)
	MOVW	R11,40(R0)
	MOVW	R12,44(R0)
	MOVW	R13,48(R0)
	MOVW	R14,52(R0)
	MOVW	SPSR, R1
	MOVW	R1, 56(R0)
	MOVW	CPSR, R2
	MOVW	R2, 60(R0)
	/* copro */
	MRC		CpMMU, 0, R3, C(CpDAC), C(0x0)
	MOVW	R3, 144(R0)
	MRC		CpMMU, 0, R3, C(CpTTB), C(0x0)
	MOVW	R3, 148(R0)
	MRC		CpMMU, 0, R3, C(CpControl), C(0x0)
	MOVW	R3, 152(R0)
	MRC		CpMMU, 0, R3, C(CpFSR), C(0x0)
	MOVW	R3, 156(R0)
	MRC		CpMMU, 0, R3, C(CpFAR), C(0x0)
	MOVW	R3, 160(R0)
	MRC		CpMMU, 0, R3, C(CpPID), C(0x0)
	MOVW	R3, 164(R0)
	/* usr */
	BIC		$(PsrMask), R2, R3
	ORR		$(0xdf), R3
	MOVW		R3, CPSR
	MOVW		SPSR, R11
	MOVW		R11, 168(R0)
	MOVW		R12, 172(R0)
	MOVW		R13, 176(R0)
	MOVW		R14, 180(R0)
	/* irq */
	BIC		$(PsrMask), R2, R3
	ORR		$(0xd2), R3
	MOVW	R3, CPSR
	MOVW	SPSR, R11
	MOVW	R11, 64(R0)
	MOVW	R12, 68(R0)
	MOVW	R13, 72(R0)
	MOVW	R14, 76(R0)
	/* und */
	BIC		$(PsrMask), R2, R3
	ORR		$(0xdb), R3
	MOVW	R3, CPSR
	MOVW	SPSR, R11
	MOVW	R11, 80(R0)
	MOVW	R12, 84(R0)
	MOVW	R13, 88(R0)
	MOVW	R14, 92(R0)
	/* abt */
	BIC		$(PsrMask), R2, R3
	ORR		$(0xd7), R3
	MOVW	R3, CPSR
	MOVW	SPSR, R11
	MOVW	R11, 96(R0)
	MOVW	R12, 100(R0)
	MOVW	R13, 104(R0)
	MOVW	R14, 108(R0)
	/* fiq */
	BIC		$(PsrMask), R2, R3
	ORR		$(0xd1), R3
	MOVW	R3, CPSR
	MOVW	SPSR, R7
	MOVW	R7, 112(R0)
	MOVW	R8, 116(R0)
	MOVW	R9, 120(R0)
	MOVW	R10,124(R0)
	MOVW	R11,128(R0)
	MOVW	R12,132(R0)
	MOVW	R13,136(R0)
	MOVW	R14,140(R0)
	/* done */
	MOVW	R2, CPSR
	MOVW	R1, SPSR
	MOVW	$0, R0
	RET

/* Entered after a resume from suspend state.
 * The bootldr jumps here after a processor reset.
 */
TEXT power_resume(SB), $-4
	MOVW	$setR12(SB), R12		/* load the SB */
	/* SVC mode, interrupts disabled */
	MOVW	$(PsrDirq|PsrDfiq|PsrMsvc), R1
	MOVW	R1, CPSR
	/* gotopowerlabel() */
	/* svc */

	MOVW	$power_state+0(SB), R0
	MOVW	56(R0), R1		/* R1: SPSR, R2: CPSR */
	MOVW	60(R0), R2
	MOVW	R1, SPSR
	MOVW	R2, CPSR
	/* copro */
	/* flush caches */
	MCR		CpMMU, 0, R0, C(CpCacheFlush), C(0x7), 0
	/* drain prefetch */
	MOVW	R0,R0						
	MOVW	R0,R0
	MOVW	R0,R0
	MOVW	R0,R0
	/* drain write buffer */
	MCR		CpMMU, 0, R0, C(CpCacheFlush), C(0xa), 4
	MCR		CpMMU, 0, R0, C(CpTLBFlush), C(0x7)
	MOVW	144(R0), R3
	MCR		CpMMU, 0, R3, C(CpDAC), C(0x0)
	MOVW	148(R0), R3
	MCR		CpMMU, 0, R3, C(CpTTB), C(0x0)
	MOVW	156(R0), R3
	MCR		CpMMU, 0, R3, C(CpFSR), C(0x0)
	MOVW	160(R0), R3
	MCR		CpMMU, 0, R3, C(CpFAR), C(0x0)
	MOVW	164(R0), R3
	MCR		CpMMU, 0, R3, C(CpPID), C(0x0)
	MOVW	152(R0), R3
	MCR		CpMMU, 0, R3, C(CpControl), C(0x0)	/* Enable cache */
	MOVW	R0,R0						
	MOVW	R0,R0
	MOVW	R0,R0
	MOVW	R0,R0
	/* flush i&d caches */
	MCR		CpMMU, 0, R0, C(CpCacheFlush), C(0x7), 0
	/* flush tlb */
	MCR		CpMMU, 0, R0, C(CpTLBFlush), C(0x7), 0
	/* drain prefetch */
	MOVW	R0,R0						
	MOVW	R0,R0
	MOVW	R0,R0
	MOVW	R0,R0
	/* usr */
	BIC		$(PsrMask), R2, R3
	ORR		$(0xdf), R3
	MOVW		168(R0), R11
	MOVW		172(R0), R12
	MOVW		176(R0), R13
	MOVW		180(R0), R14
	MOVW		R11, SPSR
	/* irq */
	BIC		$(PsrMask), R2, R3
	ORR		$(0xd2), R3
	MOVW	R3, CPSR
	MOVW	64(R0), R11
	MOVW	68(R0), R12
	MOVW	72(R0), R13
	MOVW	76(R0), R14
	MOVW	R11, SPSR
	/* und */
	BIC		$(PsrMask), R2, R3
	ORR		$(0xdb), R3
	MOVW	R3, CPSR
	MOVW	80(R0), R11
	MOVW	84(R0), R12
	MOVW	88(R0), R13
	MOVW	92(R0), R14
	MOVW	R11, SPSR
	/* abt */
	BIC		$(PsrMask), R2, R3
	ORR		$(0xd7), R3
	MOVW	R3, CPSR
	MOVW	96(R0), R11
	MOVW	100(R0), R12
	MOVW	104(R0), R13
	MOVW	108(R0), R14
	MOVW	R11, SPSR
	/* fiq */
	BIC		$(PsrMask), R2, R3
	ORR		$(0xd1), R3
	MOVW	R3, CPSR
	MOVW	112(R0), R7
	MOVW	116(R0), R8
	MOVW	120(R0), R9
	MOVW	124(R0), R10
	MOVW	128(R0), R11
	MOVW	132(R0), R12
	MOVW	136(R0), R13
	MOVW	140(R0), R14
	MOVW	R7, SPSR
	/* svc */
	MOVW	56(R0), R1
	MOVW	60(R0), R2
	MOVW	R1, SPSR
	MOVW	R2, CPSR
	MOVW	0(R0), R1
	MOVW	4(R0), R2
	MOVW	8(R0), R3
	MOVW	12(R0),R4
	MOVW	16(R0),R5
	MOVW	20(R0),R6
	MOVW	24(R0),R7
	MOVW	28(R0),R8
	MOVW	32(R0),R9
	MOVW	36(R0),R10
	MOVW	40(R0),R11
	MOVW	44(R0),R12
	MOVW	48(R0),R13
	MOVW	52(R0),R14
	RET
loop:
	B		loop

TEXT power_down(SB), $-4

	TEXT	sa1100_power_off<>+0(SB),$8
	MOVW	resetregs+0(SB),R7
	MOVW	gpioregs+0(SB),R6
	MOVW	memconfregs+0(SB),R5
	MOVW	powerregs+0(SB),R3


	/* wakeup on power | rtc */
	MOVW	$(PWR_rtc|PWR_gpio0),R2
	MOVW	R2,0xc(R3)

	/* clear reset status */
	MOVW	$(RCSR_all), R2
	MOVW	R2, 0x4(R7)
	/* float */
	MOVW	$(PCFR_opde|PCFR_fp|PCFR_fs), R2
	MOVW	R2,0x10(R3)
	/* sleep state */
	MOVW	$0,R2
	MOVW	R2,0x18(R3)
	/* set resume address (pspr)*/
	MOVW	$resumeaddr+0(SB),R1
	MOVW	0x0(R1), R2
	MOVW	R2,0x8(R3)

	BL	cacheflush(SB)

	/* disable clock switching */
	MCR   	CpPWR, 0, R1, C(CpTest), C(0x2), 2

	/* adjust mem timing */
	MOVW	memconfregs+0(SB),R5
	MOVW	0x1c(R5), R2
	ORR	$(MDREFR_k1db2), R2
	MOVW	R2, 0x1c(R5)

	/* set PLL to lower speed w/ delay (ppcr = 0)*/
	MOVW	powerregs+0(SB),R3
	MOVW	$(120*206),R0
l11:	SUB	$1,R0
	BGT	l11
	MOVW	$0, R2
	MOVW	R2, 0x14(R3)
	MOVW	$(120*206),R0
l12:	SUB	$1,R0
	BGT	l12

	/* setup registers for suspend procedure:
	 * 1. clear RT in mscx (R1, R7, R8)
	 * 2. clear DRI in mdrefr (R4)
	 * 3. set slfrsh in mdrefr (R6)
	 * 4. clear DE in mdcnfg (R9)
	 * 5. clear dram refresh (R10)
	 * 6. force sleep (R2)
	 */
	/* 1 */
	MOVW	0x10(R5), R2
	BIC	$(MSC_rt), R2
	MOVW	R2, R1
	MOVW	0x14(R5), R2
	BIC	$(MSC_rt), R2
	MOVW	R2, R7
	MOVW	0x2c(R5), R2
	BIC	$(MSC_rt), R2
	MOVW	R2, R8
	/* 2 */
	MOVW	0x1c(R5), R2
	BIC	$(0xff00), R2
	BIC	$(0x00f0), R2
	MOVW	R2, R4
	/* 3 */
	ORR	$(MDREFR_slfrsh), R2, R6
	/* 4 */
	MOVW	0x0(R5), R9
	BIC	$(MDCFNG_de), R9, R9
	/* 5 */
	MOVW	R4, R2
	BIC	$(MDREFR_slfrsh), R2, R2
	BIC	$(MDREFR_e1pin), R2, R2
	MOVW	R2, R10
	/* 6 */
	MOVW	$1,R2

TEXT power_magic(SB), $-4
	/* power_code gets copied into the area of no-ops below,
	 * at a cache-line boundary (8 instructions)
	 */
	MOVW	R0, R0
	MOVW	R0, R0
	MOVW	R0, R0
	MOVW	R0, R0
	MOVW	R0, R0
	MOVW	R0, R0
	MOVW	R0, R0
	MOVW	R0, R0
	MOVW	R0, R0
	MOVW	R0, R0
	MOVW	R0, R0
	MOVW	R0, R0
	MOVW	R0, R0
	MOVW	R0, R0
	MOVW	R0, R0
	MOVW	R0, R0

TEXT power_code(SB), $-4
	/* Follow the procedure; this code gets copied to the no-op
	 * area preceding this code
	 */
	/* 1 */
	MOVW	R1, 0x10(R5)
	MOVW	R7, 0x14(R5)
	MOVW	R8, 0x2c(R5)
	/* 2 */
	MOVW	R4, 0x1c(R5)
	/* 3 */
	MOVW	R6, 0x1c(R5)
	/* 4 */
	MOVW	R9, 0x0(R5)
	/* 5 */
	MOVW	R10, 0x1c(R5)
	/* 6 */
	MOVW	R2, 0x0(R3)
slloop:
	B		slloop			/* loop waiting for sleep */

/* The first MCR instruction of this function needs to be on a cache-line
 * boundary; to make this happen, it will be copied to the first cache-line
 * boundary 8 words from the start of doze.
 *
 * Doze puts the machine into idle mode.  Any interrupt will get it out
 * at the next instruction (the RET, to be precise).
 */
TEXT doze(SB), $-4
	MOVW	$UCDRAMZERO, R1
	MOVW	R0,R0
	MOVW	R0,R0
	MOVW	R0,R0
	MOVW	R0,R0
	MOVW	R0,R0
	MOVW	R0,R0
	MOVW	R0,R0
	MOVW	R0,R0
	MOVW	R0,R0
	MOVW	R0,R0
	MOVW	R0,R0
	MOVW	R0,R0
	MOVW	R0,R0
	MOVW	R0,R0
	MOVW	R0,R0
	MOVW	R0,R0
	MOVW	R0,R0
	MOVW	R0,R0
	MOVW	R0,R0
	MOVW	R0,R0
	MOVW	R0,R0
	MOVW	R0,R0
	MOVW	R0,R0
	MOVW	R0,R0
	RET
	
TEXT doze_code(SB), $-4
	MCR   	CpPWR, 0, R0, C(CpTest), C(0x2), 2
	MOVW	(R1), R0
	MCR  	CpPWR, 0, R0, C(CpTest), C(0x8), 2