run.c

这是一个同样来自贝尔实验室的和UNIX有着渊源的操作系统, 其简洁的设计和实现易于我们学习和理解

}

void
or(ulong ir)
{
	long v;
	int rd, rs1, rs2;

	getrop23(ir);
	if(ir&IMMBIT) {
		ximm(v, ir);
		if(trace)
			itrace("or\tr%d,#0x%x,r%d", rs1, v, rd);
	}
	else {
		v = reg.r[rs2];
		if(trace)
			itrace("or\tr%d,r%d,r%d", rs1, rs2, rd);
	}
	reg.r[rd] = reg.r[rs1] | v;
}

void
xor(ulong ir)
{
	long v;
	int rd, rs1, rs2;

	getrop23(ir);
	if(ir&IMMBIT) {
		ximm(v, ir);
		if(trace)
			itrace("xor\tr%d,#0x%x,r%d", rs1, v, rd);
	}
	else {
		v = reg.r[rs2];
		if(trace)
			itrace("xor\tr%d,r%d,r%d", rs1, rs2, rd);
	}
	reg.r[rd] = reg.r[rs1] ^ v;
}

void
xorcc(ulong ir)
{
	long v, r;
	int rd, rs1, rs2;

	getrop23(ir);
	if(ir&IMMBIT) {
		ximm(v, ir);
		if(trace)
			itrace("xorcc\tr%d,#0x%x,r%d", rs1, v, rd);
	}
	else {
		v = reg.r[rs2];
		if(trace)
			itrace("xorcc\tr%d,r%d,r%d", rs1, rs2, rd);
	}
	r = reg.r[rs1] ^ v;
	reg.psr &= ~(PSR_z|PSR_n|PSR_c|PSR_v);
	if(r == 0)
		reg.psr |= PSR_z;
	if(r < 0)
		reg.psr |= PSR_n;

	reg.r[rd] = r;
}

void
andn(ulong ir)
{
	long v;
	int rd, rs1, rs2;

	getrop23(ir);
	if(ir&IMMBIT) {
		ximm(v, ir);
		if(trace)
			itrace("andn\tr%d,#0x%x,r%d", rs1, v, rd);
	}
	else {
		v = reg.r[rs2];
		if(trace)
			itrace("andn\tr%d,r%d,r%d", rs1, rs2, rd);
	}
	reg.r[rd] = reg.r[rs1] & ~v;
}

void
andncc(ulong ir)
{
	long v, r;
	int rd, rs1, rs2;

	getrop23(ir);
	if(ir&IMMBIT) {
		ximm(v, ir);
		if(trace)
			itrace("andncc\tr%d,#0x%x,r%d", rs1, v, rd);
	}
	else {
		v = reg.r[rs2];
		if(trace)
			itrace("andncc\tr%d,r%d,r%d", rs1, rs2, rd);
	}
	r = reg.r[rs1] & ~v;
	reg.psr &= ~(PSR_z|PSR_n|PSR_c|PSR_v);
	if(r == 0)
		reg.psr |= PSR_z;
	if(r < 0)
		reg.psr |= PSR_n;

	reg.r[rd] = r;
}

void
orn(ulong ir)
{
	long v;
	int rd, rs1, rs2;

	getrop23(ir);
	if(rd == 0 && rs1 == 0)	/* ken used orn r0,r0,r0 as nop */
		nopcount++;

	if(ir&IMMBIT) {
		ximm(v, ir);
		if(trace)
			itrace("orn\tr%d,#0x%x,r%d", rs1, v, rd);
	}
	else {
		v = reg.r[rs2];
		if(trace)
			itrace("orn\tr%d,r%d,r%d", rs1, rs2, rd);
	}
	reg.r[rd] = reg.r[rs1] | ~v;
}

void
orncc(ulong ir)
{
	long r, v;
	int rd, rs1, rs2;

	getrop23(ir);
	if(ir&IMMBIT) {
		ximm(v, ir);
		if(trace)
			itrace("orncc\tr%d,#0x%x,r%d", rs1, v, rd);
	}
	else {
		v = reg.r[rs2];
		if(trace)
			itrace("orncc\tr%d,r%d,r%d", rs1, rs2, rd);
	}
	r = reg.r[rs1] | ~v;
	reg.psr &= ~(PSR_z|PSR_n|PSR_c|PSR_v);
	if(r == 0)
		reg.psr |= PSR_z;
	if(r < 0)
		reg.psr |= PSR_n;

	reg.r[rd] = r;
}

void
xnor(ulong ir)
{
	long v;
	int rd, rs1, rs2;

	getrop23(ir);
	if(ir&IMMBIT) {
		ximm(v, ir);
		if(trace)
			itrace("xnor\tr%d,#0x%x,r%d", rs1, v, rd);
	}
	else {
		v = reg.r[rs2];
		if(trace)
			itrace("xnor\tr%d,r%d,r%d", rs1, rs2, rd);
	}
	reg.r[rd] = reg.r[rs1] ^ ~v;
}

void
xnorcc(ulong ir)
{
	long v, r;
	int rd, rs1, rs2;

	getrop23(ir);
	if(ir&IMMBIT) {
		ximm(v, ir);
		if(trace)
			itrace("xnorcc\tr%d,#0x%x,r%d", rs1, v, rd);
	}
	else {
		v = reg.r[rs2];
		if(trace)
			itrace("xnorcc\tr%d,r%d,r%d", rs1, rs2, rd);
	}
	r = reg.r[rs1] ^ ~v;
	reg.psr &= ~(PSR_z|PSR_n|PSR_c|PSR_v);
	if(r == 0)
		reg.psr |= PSR_z;
	if(r < 0)
		reg.psr |= PSR_n;

	reg.r[rd] = r;
}

void
st(ulong ir)
{
	ulong ea;
	int rd, rs1, rs2;

	getrop23(ir);
	if(ir&IMMBIT) {
		ximm(ea, ir);
		if(trace)
			itrace("st\tr%d,0x%lux(r%d) %lux=%lux",
					rd, ea, rs1, ea+reg.r[rs1], reg.r[rd]);
		ea += reg.r[rs1];
	}
	else {
		ea = reg.r[rs1] + reg.r[rs2];
		if(trace)
			itrace("st\tr%d,[r%d+r%d] %lux=%lux",
					rd, rs1, rs2, ea, reg.r[rd]);
	}

	putmem_w(ea, reg.r[rd]);
}

void
std(ulong ir)
{
	ulong ea;
	int rd, rs1, rs2;

	getrop23(ir);
	if(ir&IMMBIT) {
		ximm(ea, ir);
		if(trace)
			itrace("std\tr%d,0x%lux(r%d) %lux=%lux",
					rd, ea, rs1, ea+reg.r[rs1], reg.r[rd]);
		ea += reg.r[rs1];
	}
	else {
		ea = reg.r[rs1] + reg.r[rs2];
		if(trace)
			itrace("std\tr%d,[r%d+r%d] %lux=%lux",
					rd, rs1, rs2, ea, reg.r[rd]);
	}

	putmem_w(ea, reg.r[rd]);
	putmem_w(ea+4, reg.r[rd+1]);
}

void
stb(ulong ir)
{
	ulong ea;
	int rd, rs1, rs2;

	getrop23(ir);
	if(ir&IMMBIT) {
		ximm(ea, ir);
		if(trace)
			itrace("stb\tr%d,0x%lux(r%d) %lux=%lux",
					rd, ea, rs1, ea+reg.r[rs1], reg.r[rd]&0xff);
		ea += reg.r[rs1];
	}
	else {
		ea = reg.r[rs1] + reg.r[rs2];
		if(trace)
			itrace("stb\tr%d,[r%d+r%d] %lux=%lux",
					rd, rs1, rs2, ea, reg.r[rd]&0xff);
	}

	putmem_b(ea, reg.r[rd]);
}

void
sth(ulong ir)
{
	ulong ea;
	int rd, rs1, rs2;

	getrop23(ir);
	if(ir&IMMBIT) {
		ximm(ea, ir);
		if(trace)
			itrace("sth\tr%d,0x%lux(r%d) %lux=%lux",
					rd, ea, rs1, ea+reg.r[rs1], reg.r[rd]&0xffff);
		ea += reg.r[rs1];
	}
	else {
		ea = reg.r[rs1] + reg.r[rs2];
		if(trace)
			itrace("sth\tr%d,[r%d+r%d] %lux=%lux",
					rd, rs1, rs2, ea, reg.r[rd]&0xffff);
	}

	putmem_h(ea, reg.r[rd]);
}

void
ld(ulong ir)
{
	ulong ea;
	int rd, rs1, rs2;

	getrop23(ir);
	if(ir&IMMBIT) {
		ximm(ea, ir);
		if(trace)
			itrace("ld\tr%d,0x%lux(r%d) ea=%lux",rd, ea, rs1, ea+reg.r[rs1]);
		ea += reg.r[rs1];
	}
	else {
		ea = reg.r[rs1] + reg.r[rs2];
		if(trace)
			itrace("ld\tr%d,[r%d+r%d] ea=%lux", rd, rs1, rs2, ea);
	}

	reg.r[rd] = getmem_w(ea);
	ilock(rd);
}

void
swap(ulong ir)
{
	ulong t, ea;
	int rd, rs1, rs2;

	getrop23(ir);
	if(ir&IMMBIT) {
		ximm(ea, ir);
		if(trace)
			itrace("swap\tr%d,0x%lux(r%d) ea=%lux",
						rd, ea, rs1, ea+reg.r[rs1]);
		ea += reg.r[rs1];
	}
	else {
		ea = reg.r[rs1] + reg.r[rs2];
		if(trace)
			itrace("swap\tr%d,[r%d+r%d] ea=%lux", rd, rs1, rs2, ea);
	}

	t = reg.r[rd];
	reg.r[rd] = getmem_w(ea);
	putmem_w(ea, t);
}

void
ldd(ulong ir)
{
	ulong ea;
	int rd, rs1, rs2;

	getrop23(ir);
	if(ir&IMMBIT) {
		ximm(ea, ir);
		if(trace)
			itrace("ldd\tr%d,0x%lux(r%d) ea=%lux",rd, ea, rs1, ea+reg.r[rs1]);
		ea += reg.r[rs1];
	}
	else {
		ea = reg.r[rs1] + reg.r[rs2];
		if(trace)
			itrace("ldd\tr%d,[r%d+r%d] ea=%lux", rd, rs1, rs2, ea);
	}

	reg.r[rd] = getmem_w(ea);
	reg.r[rd+1] = getmem_w(ea+4);
}

void
ldub(ulong ir)
{
	ulong ea;
	int rd, rs1, rs2;

	getrop23(ir);
	if(ir&IMMBIT) {
		ximm(ea, ir);
		if(trace)
			itrace("ldub\tr%d,0x%lux(r%d) ea=%lux",
						rd, ea, rs1, ea+reg.r[rs1]);
		ea += reg.r[rs1];
	}
	else {
		ea = reg.r[rs1] + reg.r[rs2];
		if(trace)
			itrace("ldub\tr%d,[r%d+r%d] ea=%lux", rd, rs1, rs2, ea);
	}

	reg.r[rd] = getmem_b(ea) & 0xff;
	ilock(rd);
}

void
ldstub(ulong ir)
{
	ulong ea;
	int rd, rs1, rs2;

	getrop23(ir);
	if(ir&IMMBIT) {
		ximm(ea, ir);
		if(trace)
			itrace("ldstub\tr%d,0x%lux(r%d) ea=%lux",
						rd, ea, rs1, ea+reg.r[rs1]);
		ea += reg.r[rs1];
	}
	else {
		ea = reg.r[rs1] + reg.r[rs2];
		if(trace)
			itrace("ldstub\tr%d,[r%d+r%d] ea=%lux", rd, rs1, rs2, ea);
	}

	reg.r[rd] = getmem_b(ea) & 0xff;
	putmem_b(ea, 0xff);
}

void
ldsb(ulong ir)
{
	ulong ea;
	int rd, rs1, rs2;

	getrop23(ir);
	if(ir&IMMBIT) {
		ximm(ea, ir);
		if(trace)
			itrace("ldsb\tr%d,0x%lux(r%d) ea=%lux",
						rd, ea, rs1, ea+reg.r[rs1]);
		ea += reg.r[rs1];
	}
	else {
		ea = reg.r[rs1] + reg.r[rs2];
		if(trace)
			itrace("ldsb\tr%d,[r%d+r%d] ea=%lux", rd, rs1, rs2, ea);
	}

	reg.r[rd] = (schar)getmem_b(ea);
	ilock(rd);
}

void
lduh(ulong ir)
{
	ulong ea;
	int rd, rs1, rs2;

	getrop23(ir);
	if(ir&IMMBIT) {
		ximm(ea, ir);
		if(trace)
			itrace("lduh\tr%d,0x%lux(r%d) ea=%lux",
						rd, ea, rs1, ea+reg.r[rs1]);
		ea += reg.r[rs1];
	}
	else {
		ea = reg.r[rs1] + reg.r[rs2];
		if(trace)
			itrace("lduh\tr%d,[r%d+r%d] ea=%lux", rd, rs1, rs2, ea);
	}

	reg.r[rd] = getmem_h(ea) & 0xffff;
	ilock(rd);
}

void
ldsh(ulong ir)
{
	ulong ea;
	int rd, rs1, rs2;

	getrop23(ir);
	if(ir&IMMBIT) {
		ximm(ea, ir);
		if(trace)
			itrace("ldsh\tr%d,0x%lux(r%d) ea=%lux",
						rd, ea, rs1, ea+reg.r[rs1]);
		ea += reg.r[rs1];
	}
	else {
		ea = reg.r[rs1] + reg.r[rs2];
		if(trace)
			itrace("ldsh\tr%d,[r%d+r%d] ea=%lux", rd, rs1, rs2, ea);
	}

	reg.r[rd] = (short)getmem_h(ea);
	ilock(rd);
}

void
sethi(ulong ir)
{
	int rd;
	ulong v;

	rd = (ir>>25)&0x1f;
	v = (ir&0x3FFFFF)<<10;

	if(rd == 0)
		nopcount++;

	if(trace)
		itrace("sethi\t0x%lux,r%d", v, rd);

	reg.r[rd] = v;
}

void
call(ulong ir)
{
	Symbol s;
	ulong npc;

	npc = (ir<<2) + reg.pc;
	if(trace)
		itrace("call\t%lux", npc);

	ci->taken++;
	reg.r[15] = reg.pc;
	reg.ir = ifetch(reg.pc+4);
	delay(npc);

	if(calltree) {
		findsym(npc, CTEXT, &s);
		Bprint(bioout, "%8lux %s(", reg.pc, s.name);
		printparams(&s, reg.r[1]);
		Bprint(bioout, "from ");
		printsource(reg.pc);
		Bputc(bioout, '\n');
	}
	npc -= 4;
	reg.pc = npc;
}

void
jmpl(ulong ir)
{
	ulong ea, o;
	Symbol s;
	int rd, rs1, rs2;

	getrop23(ir);
	if(ir&IMMBIT) {
		ximm(ea, ir);
		o = ea;
		if(trace)
			itrace("jmpl\t0x%lux(r%d),r%d", ea, rs1, rd);

		ea += reg.r[rs1];
		if(calltree && rd == 0 && o == 8) {
			findsym(ea-4, CTEXT, &s);
			Bprint(bioout, "%8lux return to %lux %s r7=%lux\n",
						reg.pc, ea-4, s.name, reg.r[7]);
		}
	}
	else {
		ea = reg.r[rs1] + reg.r[rs2];
		if(trace)
			itrace("jmpl\t[r%d+r%d],r%d", rs1, rs2, rd);
	}

	ci->taken++;
	reg.r[rd] = reg.pc;
	reg.ir = ifetch(reg.pc+4);
	delay(ea);
	reg.pc = ea-4;
}

void
bicc(ulong ir)
{
	char *op;
	ulong npc, anul, ba;
	int takeit, z, v, n, c;

	SET(op, takeit);
	ba = 0;
	switch((ir>>25)&0x0F) {
	case 0:
		op = "bn";
		takeit = 0;
		break;
	case 1:
		op = "be";
		takeit = reg.psr&PSR_z;
		break;
	case 2:
		op = "ble";
		z = reg.psr&PSR_z ? 1 : 0;
		v = reg.psr&PSR_v ? 1 : 0;
		n = reg.psr&PSR_n ? 1 : 0;
		takeit = z | (n ^ v);
		break;
	case 3:
		op = "bl";
		v = reg.psr&PSR_v ? 1 : 0;
		n = reg.psr&PSR_n ? 1 : 0;
		takeit = n ^ v;
		break;
	case 4:
		op = "bleu";
		z = reg.psr&PSR_z ? 1 : 0;
		c = reg.psr&PSR_c ? 1 : 0;
		takeit = c | z;
		break;
	case 5:
		op = "bcs";
		takeit = reg.psr&PSR_c;
		break;
	case 6:
		op = "bneg";
		takeit = reg.psr&PSR_n;
		break;
	case 7:
		op = "bvs";
		takeit = reg.psr&PSR_v;
		break;
	case 8:
		op = "ba";
		ba = 1;
		takeit = 1;
		break;
	case 9:
		op = "bne";
		takeit = !(reg.psr&PSR_z);
		break;
	case 10:
		op = "bg";
		z = reg.psr&PSR_z ? 1 : 0;
		v = reg.psr&PSR_v ? 1 : 0;
		n = reg.psr&PSR_n ? 1 : 0;
		takeit = !(z | (n ^ v));
		break;
	case 11:
		op = "bge";
		v = reg.psr&PSR_v ? 1 : 0;
		n = reg.psr&PSR_n ? 1 : 0;
		takeit = !(n ^ v);
		break;
	case 12:
		op = "bgu";
		z = reg.psr&PSR_z ? 1 : 0;
		c = reg.psr&PSR_c ? 1 : 0;
		takeit = !(c | z);
		break;
	case 13:
		op = "bcc";
		takeit = !(reg.psr&PSR_c);
		break;
	case 14:
		op = "bpos";
		takeit = !(reg.psr&PSR_n);
		break;
	case 15:
		op = "bvc";
		takeit = !(reg.psr&PSR_v);
		break;
	}

	npc = ir & 0x3FFFFF;
	if(npc & (1<<21))
		npc |= ~((1<<22)-1);
	npc = (npc<<2) + reg.pc;

	anul = ir&ANUL;
	if(trace) {
		if(anul)
			itrace("%s,a\t%lux", op, npc);
		else
			itrace("%s\t%lux", op, npc);
	}

	if(takeit == 0) {
		reg.pc += 4;
		if(anul == 0) {
			reg.ir = ifetch(reg.pc);
			delay(reg.pc+4);
		}
		else
			anulled++;
		return;
	}

	ci->taken++;
	if(ba && anul) {
		anulled++;
		reg.pc = npc-4;
		return;	
	}
	reg.ir = ifetch(reg.pc+4);
	delay(npc);
	reg.pc = npc-4;
}