run.c

这是一个同样来自贝尔实验室的和UNIX有着渊源的操作系统, 其简洁的设计和实现易于我们学习和理解

#include <u.h>
#include <libc.h>
#include <bio.h>
#include <mach.h>
#define Extern extern
#include "sparc.h"

void add(ulong);
void and(ulong);
void or(ulong);
void xor(ulong);
void sub(ulong);
void andn(ulong);
void xnor(ulong);
void subcc(ulong);
void sll(ulong);
void srl(ulong);
void sra(ulong);
void jmpl(ulong);
void andcc(ulong);
void xorcc(ulong);
void andncc(ulong);
void wry(ulong);
void rdy(ulong);
void mulscc(ulong);
void fcmp(ulong);
void farith(ulong);
void addcc(ulong);
void addx(ulong);
void addxcc(ulong);
void orcc(ulong);
void orncc(ulong);
void xnorcc(ulong);
void orn(ulong);

Inst op2[] = {
	{ add,		"add",	Iarith },
	{ and,		"and",	Iarith },
	{ or,		"or",	Iarith },
	{ xor,		"xor",	Iarith },
	{ sub,		"sub",	Iarith },
	{ andn,		"andn", Iarith },
	{ orn,		"orn",	Inop },
	{ xnor,		"xnor", Iarith },
	{ addx,		"addx", Iarith },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ addcc, 	"addcc", Iarith },
	{ andcc, 	"andcc", Iarith },
	{ orcc,	 	"orcc",  Iarith },
	{ xorcc, 	"xorcc", Iarith },
	{ subcc, 	"subcc", Iarith },
	{ andncc,	"andncc",Iarith },
	{ orncc, 	"orncc", Iarith },
	{ xnorcc,	"xnorcc",Iarith },
	{ addxcc,	"addxcc",Iarith },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ mulscc,	"mulscc", Iarith },
	{ sll,		"sll",	Iarith },
	{ srl,		"srl",	Iarith },
	{ sra,		"sra",	Iarith },
	{ rdy,		"rdy",	Ireg },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ wry,		"wry",	Ireg },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ farith,	"farith", Ifloat },
	{ fcmp,		"fcmp", Ifloat },
	{ undef,	"" },
	{ undef,	"" },
	{ jmpl,		"jmpl", Ibranch },
	{ undef,	"" },
	{ ta,		"ta",	Isyscall },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ 0 }
};

void st(ulong);
void stb(ulong);
void sth(ulong);
void ld(ulong);
void ldub(ulong);
void ldsb(ulong);
void lduh(ulong);
void stf(ulong);
void ldf(ulong);
void ldsh(ulong);
void std(ulong);
void ldd(ulong);
void ldstub(ulong);
void swap(ulong);
void lddf(ulong);
void stdf(ulong);

Inst op3[] = {
	{ ld,		"ld",	Iload },
	{ ldub,		"ldub",	Iload },
	{ lduh,		"lduh",	Iload },
	{ ldd,		"ldd",	Iload },
	{ st,		"st",	Istore },
	{ stb,		"stb",	Istore },
	{ sth,		"sth",	Istore },
	{ std,		"std",	Istore },
	{ undef,	"" },
	{ ldsb,		"ldsb",	Iload },
	{ ldsh,		"ldsh", Iload },
	{ undef,	"" },
	{ undef,	"" },
	{ ldstub,	"ldstub", Iload },
	{ undef,	"" },
	{ swap,		"swap",	Iload },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ ldf,		"ldf",	Ifloat },
	{ undef,	"" },
	{ undef,	"" },
	{ lddf,		"lddf", Ifloat },
	{ stf,		"stf",	Ifloat },
	{ undef,	"" },
	{ undef,	"" },
	{ stdf,		"stdf",	Ifloat },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ undef,	"" },
	{ 0 }
};

void sethi(ulong);
void bicc(ulong);
void fbcc(ulong);
void call(ulong);

Inst op0[] = {
	{ undef,	"" },
	{ undef,	"" },
	{ bicc,		"bicc",	Ibranch },
	{ undef,	"" },
	{ sethi,	"sethi",Iarith },
	{ undef,	"" },
	{ fbcc,		"fbcc",	Ibranch },
	{ undef,	"" },
	/* This is a fake and connot be reached by op0 decode */
	{ call,		"call", Ibranch },
	{ 0 }
};

void call(ulong);

void
run(void)
{
	do {
		reg.r[0] = 0;
		reg.ir = ifetch(reg.pc);
		switch(reg.ir>>30) {
		case 0:
			ci = &op0[(reg.ir>>22)&0x07];
			ci->count++;
			(*ci->func)(reg.ir);
			break;
		case 1:
			ci = &op0[8];
			ci->count++;
			call(reg.ir);
			break;
		case 2:
			ci = &op2[(reg.ir>>19)&0x3f];
			ci->count++;
			(*ci->func)(reg.ir);
			break;
		case 3:
			ci = &op3[(reg.ir>>19)&0x3f];
			ci->count++;
			(*ci->func)(reg.ir);
			break;
		}
		reg.pc += 4;
		if(bplist)
			brkchk(reg.pc, Instruction);
	}while(--count);
}

void
ilock(int rd)
{
	ulong ir;

	ir = getmem_4(reg.pc+4);
	switch(ir>>30) {
	case 0:
	case 1:
		break;
	case 2:
		if(((ir>>20)&0x1f) == 0x1a)		/* floating point */
			break;
	case 3:
		if(rd == ((ir>>14)&0x1f)) {
			loadlock++;
			break;
		}
		if(ir&IMMBIT)
			break;
		if(rd == (ir&0x1f))
			loadlock++;
		break;
	}
}

void
delay(ulong npc)
{
	ulong opc;

	reg.r[0] = 0;
	if(reg.ir != NOP)
		ci->useddelay++;
	switch(reg.ir>>30) {
	case 0:
		ci = &op0[(reg.ir>>22)&0x07];
		ci->count++;
		(*ci->func)(reg.ir);
		break;
	case 1:
		ci = &op0[8];
		ci->count++;
		call(reg.ir);
		break;
	case 2:
		ci = &op2[(reg.ir>>19)&0x3f];
		ci->count++;
		opc = reg.pc;
		reg.pc = npc-4;
		(*ci->func)(reg.ir);
		reg.pc = opc;
		break;
	case 3:
		ci = &op3[(reg.ir>>19)&0x3f];
		ci->count++;
		opc = reg.pc;
		reg.pc = npc-4;
		(*ci->func)(reg.ir);
		reg.pc = opc;
		break;
	}
}

void
undef(ulong ir)
{
/*	Bprint(bioout, "op=%d op2=%d op3=%d\n", ir>>30, (ir>>21)&0x7, (ir>>19)&0x3f); */
	Bprint(bioout, "illegal_instruction IR #%.8lux\n", ir);
	longjmp(errjmp, 0);
}

void
sub(ulong ir)
{
	long v;
	int rd, rs1, rs2;

	getrop23(ir);
	if(ir&IMMBIT) {
		ximm(v, ir);
		if(trace)
			itrace("sub\tr%d,#0x%x,r%d", rs1, v, rd);
	}
	else {
		v = reg.r[rs2];
		if(trace)
			itrace("sub\tr%d,r%d,r%d", rs1, rs2, rd);
	}
	reg.r[rd] = reg.r[rs1] - v;
}

void
sll(ulong ir)
{
	long v;
	int rd, rs1, rs2;

	getrop23(ir);
	if(ir&IMMBIT) {
		ximm(v, ir);
		if(trace)
			itrace("sll\tr%d,#0x%x,r%d", rs1, v, rd);
	}
	else {
		v = reg.r[rs2]&0x1F;
		if(trace)
			itrace("sll\tr%d,r%d,r%d", rs1, rs2, rd);
	}
	reg.r[rd] = reg.r[rs1] << v;
}

void
srl(ulong ir)
{
	long v;
	int rd, rs1, rs2;

	getrop23(ir);
	if(ir&IMMBIT) {
		ximm(v, ir);
		if(trace)
			itrace("srl\tr%d,#0x%x,r%d", rs1, v, rd);
	}
	else {
		v = reg.r[rs2];
		if(trace)
			itrace("srl\tr%d,r%d,r%d", rs1, rs2, rd);
	}
	reg.r[rd] = (ulong)reg.r[rs1] >> v;
}

void
sra(ulong ir)
{
	long v;
	int rd, rs1, rs2;

	getrop23(ir);
	if(ir&IMMBIT) {
		ximm(v, ir);
		if(trace)
			itrace("sra\tr%d,#0x%x,r%d", rs1, v, rd);
	}
	else {
		v = reg.r[rs2];
		if(trace)
			itrace("sra\tr%d,r%d,r%d", rs1, rs2, rd);
	}
	if(reg.r[rs1]&SIGNBIT)
		reg.r[rd] = reg.r[rs1]>>v | ~((1<<(32-v))-1);
	else
		reg.r[rd] = reg.r[rs1]>>v;
}

void
subcc(ulong ir)
{
	long v;
	int b31rs1, b31op2, b31res, r, rd, rs1, rs2;

	getrop23(ir);
	if(ir&IMMBIT) {
		ximm(v, ir);
		if(trace)
			itrace("subcc\tr%d,#0x%x,r%d", rs1, v, rd);
	}
	else {
		v = reg.r[rs2];
		if(trace)
			itrace("subcc\tr%d,r%d,r%d", rs1, rs2, rd);
	}
	r = reg.r[rs1] - v;
	reg.psr &= ~(PSR_z|PSR_n|PSR_c|PSR_v);
	if(r == 0)
		reg.psr |= PSR_z;
	if(r < 0)
		reg.psr |= PSR_n;

	b31rs1 = reg.r[rs1]>>31;
	b31op2 = v>>31;
	b31res = r>>31;

	if((b31rs1 & ~b31op2 & ~b31res)|(~b31rs1 & b31op2 & b31res))
		reg.psr |= PSR_v;

	if((~b31rs1 & b31op2)|(b31res & (~b31rs1|b31op2)))
		reg.psr |= PSR_c;

	reg.r[rd] = r;

}

void
add(ulong ir)
{
	long v;
	int rd, rs1, rs2;

	getrop23(ir);
	if(ir&IMMBIT) {
		ximm(v, ir);
		if(trace)
			itrace("add\tr%d,#0x%x,r%d", rs1, v, rd);
	}
	else {
		v = reg.r[rs2];
		if(trace)
			itrace("add\tr%d,r%d,r%d", rs1, rs2, rd);
	}
	reg.r[rd] = reg.r[rs1] + v;
}

void
addcc(ulong ir)
{
	long v, r;
	int rd, rs1, rs2, b31rs1, b31op2, b31r;

	getrop23(ir);
	if(ir&IMMBIT) {
		ximm(v, ir);
		if(trace)
			itrace("addcc\tr%d,#0x%x,r%d", rs1, v, rd);
	}
	else {
		v = reg.r[rs2];
		if(trace)
			itrace("addcc\tr%d,r%d,r%d", rs1, rs2, rd);
	}
	r = reg.r[rs1] + v;
	reg.psr &= ~(PSR_z|PSR_n|PSR_c|PSR_v);
	if(r == 0)
		reg.psr |= PSR_z;
	if(r < 0)
		reg.psr |= PSR_n;

	b31rs1 = reg.r[rs1]>>31;
	b31op2 = v>>31;
	b31r = r>>31;
	if((b31rs1 & b31op2 & ~b31r)|(~b31rs1 & ~b31op2 & b31r))
		reg.psr |= PSR_v;
	if((b31rs1 & b31op2) | (~b31r & (b31rs1 | b31op2)))
		reg.psr |= PSR_c;

	reg.r[rd] = r;
}

void
addx(ulong ir)
{
	long v;
	int rd, rs1, rs2;

	getrop23(ir);
	if(ir&IMMBIT) {
		ximm(v, ir);
		if(trace)
			itrace("addx\tr%d,#0x%x,r%d", rs1, v, rd);
	}
	else {
		v = reg.r[rs2];
		if(trace)
			itrace("addx\tr%d,r%d,r%d", rs1, rs2, rd);
	}
	if(reg.psr&PSR_c)
		v++;
	reg.r[rd] = reg.r[rs1] + v;
}

void
addxcc(ulong ir)
{
	long r, v;
	int rd, rs1, rs2, b31rs1, b31op2, b31r;

	getrop23(ir);
	if(ir&IMMBIT) {
		ximm(v, ir);
		if(trace)
			itrace("addxcc\tr%d,#0x%x,r%d", rs1, v, rd);
	}
	else {
		v = reg.r[rs2];
		if(trace)
			itrace("addxcc\tr%d,r%d,r%d", rs1, rs2, rd);
	}
	if(reg.psr&PSR_c)
		v++;

	r = reg.r[rs1] + v;
	reg.psr &= ~(PSR_z|PSR_n|PSR_c|PSR_v);
	if(r == 0)
		reg.psr |= PSR_z;
	if(r < 0)
		reg.psr |= PSR_n;

	b31rs1 = reg.r[rs1]>>31;
	b31op2 = v>>31;
	b31r = r>>31;
	if((b31rs1 & b31op2 & ~b31r)|(~b31rs1 & ~b31op2 & b31r))
		reg.psr |= PSR_v;
	if((b31rs1 & b31op2) | (~b31r & (b31rs1 | b31op2)))
		reg.psr |= PSR_c;

	reg.r[rd] = r;
}

void
wry(ulong ir)
{
	long v;
	int rd, rs1, rs2;

	getrop23(ir);
	if(rd != 0)
		undef(ir);
	if(ir&IMMBIT) {
		ximm(v, ir);
		if(trace)
			itrace("wry\tr%d,#0x%x,Y", rs1, v);
	}
	else {
		v = reg.r[rs2];
		if(trace)
			itrace("wry\tr%d,r%d,Y", rs1, rs2);
	}
	reg.Y = reg.r[rs1] + v;
}

void
rdy(ulong ir)
{
	int rd, rs1, rs2;

	getrop23(ir);
	USED(rs2);
	if(rs1 != 0)
		undef(ir);
	
	if(trace)
		itrace("rdy\tY,r%d", rd);

	reg.r[rd] = reg.Y;
}

void
and(ulong ir)
{
	long v;
	int rd, rs1, rs2;

	getrop23(ir);
	if(ir&IMMBIT) {
		ximm(v, ir);
		if(trace)
			itrace("and\tr%d,#0x%x,r%d", rs1, v, rd);
	}
	else {
		v = reg.r[rs2];
		if(trace)
			itrace("and\tr%d,r%d,r%d", rs1, rs2, rd);
	}
	reg.r[rd] = reg.r[rs1] & v;
}

void
andcc(ulong ir)
{
	long v, r;
	int rd, rs1, rs2;

	getrop23(ir);
	if(ir&IMMBIT) {
		ximm(v, ir);
		if(trace)
			itrace("andcc\tr%d,#0x%x,r%d", rs1, v, rd);
	}
	else {
		v = reg.r[rs2];
		if(trace)
			itrace("andcc\tr%d,r%d,r%d", rs1, rs2, rd);
	}
	r = reg.r[rs1] & v;
	reg.psr &= ~(PSR_z|PSR_n|PSR_c|PSR_v);
	if(r == 0)
		reg.psr |= PSR_z;
	if(r < 0)
		reg.psr |= PSR_n;

	reg.r[rd] = r;
}

void
orcc(ulong ir)
{
	long v, r;
	int rd, rs1, rs2;

	getrop23(ir);
	if(ir&IMMBIT) {
		ximm(v, ir);
		if(trace)
			itrace("orcc\tr%d,#0x%x,r%d", rs1, v, rd);
	}
	else {
		v = reg.r[rs2];
		if(trace)
			itrace("orcc\tr%d,r%d,r%d", rs1, rs2, rd);
	}
	r = reg.r[rs1] | v;
	reg.psr &= ~(PSR_z|PSR_n|PSR_c|PSR_v);
	if(r == 0)
		reg.psr |= PSR_z;
	if(r < 0)
		reg.psr |= PSR_n;

	reg.r[rd] = r;
}

void
mulscc(ulong ir)
{
	int b, n, v, rd, rs1, rs2;
	long o1, o2, r, b31o1, b31o2, b31r;

	getrop23(ir);
	if(ir&IMMBIT) {
		ximm(o2, ir);
		if(trace)
			itrace("mulscc\tr%d,#0x%x,r%d", rs1, o2, rd);
	}
	else {
		o2 = reg.r[rs2];
		if(trace)
			itrace("mulscc\tr%d,r%d,r%d", rs1, rs2, rd);
	}
	o1 = reg.r[rs1]>>1;
	n = reg.psr&PSR_n ? 1 : 0;
	v = reg.psr&PSR_v ? 1 : 0;

	o1 |= (n ^ v)<<31;
	if((reg.Y&1) == 0)
		o2 = 0;

	r = o1 + o2;
	reg.psr &= ~(PSR_z|PSR_n|PSR_c|PSR_v);
	if(r == 0)
		reg.psr |= PSR_z;
	if(r < 0)
		reg.psr |= PSR_n;

	b31o1 = o1>>31;
	b31o2 = o2>>31;
	b31r = r>>31;
	if((b31o1 & b31o2 & ~b31r) | (~b31o1 & ~b31o2 & b31r))
		reg.psr |= PSR_v;
	if((b31o1 & b31o2) | (~b31r & (b31o1 | b31o2)))		
		reg.psr |= PSR_c;

	b = reg.r[rs1]&1;
	reg.Y = (reg.Y>>1)|(b<<31);
	reg.r[rd] = r;