📄 timing
字号:
units branch integer floating pointon 601 issue at most one per unit per cycle eight entry instruction queue can fill queue from cache in one clock cycle loads from requested address to end of cache blockpipeline prefetch includes ins. cache access cycles decode execute writebackfpu IQ[3210] → fpu buffer/decode [≥1 cycle] → execute 1 → execute 2 → writebackiu IQ0/decode → buffer [if exec busy] → execute [hold for dependency] → circulate in load/store writebackbpu IQ[3210] → decode/execute → writebacknotes address calculation must complete before stored value enters write buffer
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -