iu.c

这是一个同样来自贝尔实验室的和UNIX有着渊源的操作系统, 其简洁的设计和实现易于我们学习和理解

	ulong ea;
	int ra, rd, upd;
	long imm;

	getairr(ir);
	ea = imm;
	upd = (ir&(1L<<26))!=0;
	if(ra) {
		ea += reg.r[ra];
		if(upd)
			reg.r[ra] = ea;
	} else {
		if(upd)
			undef(ir);
	}
	if(trace)
		itrace("%s\tr%d,%ld(r%d) #%lux=#%lux (%ld)",
					ci->name, rd, imm, ra, ea, reg.r[rd], reg.r[rd]);
	putmem_w(ea, reg.r[rd]);

}

void
stwx(ulong ir)
{
	ulong ea;
	int ra, rd, upd, rb;

	getarrr(ir);
	ea = reg.r[rb];
	upd = getxo(ir)==183;
	if(ra) {
		ea += reg.r[ra];
		if(upd)
			reg.r[ra] = ea;
		if(trace)
			itrace("%s\tr%d,(r%d+r%d) #%lux=#%lux (%ld)",
					ci->name, rd, ra, rb, ea, reg.r[rd], reg.r[rd]);
	} else {
		if(upd)
			undef(ir);
		if(trace)
			itrace("%s\tr%d,(r%d) #%lux=#%lux (%ld)",
					ci->name, rd, rb, ea, reg.r[rd], reg.r[rd]);
	}
	putmem_w(ea, reg.r[rd]);

}

void
stwcx(ulong ir)
{
	ulong ea;
	int ra, rd, rb;

	if((ir & Rc) == 0)
		undef(ir);
	getarrr(ir);
	ea = reg.r[rb];
	if(ra) {
		ea += reg.r[ra];
		if(trace)
			itrace("%s\tr%d,(r%d+r%d) #%lux=#%lux (%ld)",
					ci->name, rd, ra, rb, ea, reg.r[rd], reg.r[rd]);
	} else {
		if(trace)
			itrace("%s\tr%d,(r%d) #%lux=#%lux (%ld)",
					ci->name, rd, rb, ea, reg.r[rd], reg.r[rd]);
	}
	putmem_w(ea, reg.r[rd]);	/* assume a reservation exists; store succeeded */
	setcr(0, 0);

}

void
stb(ulong ir)
{
	ulong ea;
	int ra, rd, upd, v;
	long imm;

	getairr(ir);
	ea = imm;
	upd = (ir&(1L<<26))!=0;
	if(ra) {
		ea += reg.r[ra];
		if(upd)
			reg.r[ra] = ea;
	} else {
		if(upd)
			undef(ir);
	}
	v = reg.r[rd] & 0xFF;
	if(trace)
		itrace("%s\tr%d,%ld(r%d) #%lux=#%lux (%ld)",
					ci->name, rd, imm, ra, ea, v, v);
	putmem_b(ea, v);
}

void
stbx(ulong ir)
{
	ulong ea;
	int ra, rd, upd, rb, v;

	getarrr(ir);
	ea = reg.r[rb];
	upd = getxo(ir)==247;
	v = reg.r[rd] & 0xFF;
	if(ra) {
		ea += reg.r[ra];
		if(upd)
			reg.r[ra] = ea;
		if(trace)
			itrace("%s\tr%d,(r%d+r%d) #%lux=#%lux (%ld)",
					ci->name, rd, ra, rb, ea, v, v);
	} else {
		if(upd)
			undef(ir);
		if(trace)
			itrace("%s\tr%d,(r%d) #%lux=#%lux (%ld)",
					ci->name, rd, rb, ea, v, v);
	}
	putmem_b(ea, v);

}

void
lhz(ulong ir)
{
	ulong ea;
	int imm, ra, rd, upd;

	getairr(ir);
	ea = imm;
	upd = (ir&(1L<<26))!=0;
	if(ra) {
		ea += reg.r[ra];
		if(upd)
			reg.r[ra] = ea;
	} else {
		if(upd)
			undef(ir);
	}
	if(trace)
		itrace("%s\tr%d,%ld(r%d) ea=%lux", ci->name, rd, imm, ra, ea);

	reg.r[rd] = getmem_h(ea);
}

void
lhzx(ulong ir)
{
	ulong ea;
	int rb, ra, rd, upd;

	getarrr(ir);
	ea = reg.r[rb];
	upd = getxo(ir)==311;
	if(ra) {
		ea += reg.r[ra];
		if(upd)
			reg.r[ra] = ea;
		if(trace)
			itrace("%s\tr%d,(r%d+r%d) ea=%lux", ci->name, rd, ra, rb, ea);
	} else {
		if(upd)
			undef(ir);
		if(trace)
			itrace("%s\tr%d,(r%d) ea=%lux", ci->name, rd, rb, ea);
	}

	reg.r[rd] = getmem_h(ea);
}

void
lha(ulong ir)
{
	ulong ea;
	int imm, ra, rd, upd;

	getairr(ir);
	ea = imm;
	upd = (ir&(1L<<26))!=0;
	if(ra) {
		ea += reg.r[ra];
		if(upd)
			reg.r[ra] = ea;
	} else {
		if(upd)
			undef(ir);
	}
	if(trace)
		itrace("%s\tr%d,%ld(r%d) ea=%lux", ci->name, rd, imm, ra, ea);

	reg.r[rd] = (short)getmem_h(ea);
}

void
lhax(ulong ir)
{
	ulong ea;
	int rb, ra, rd, upd;

	getarrr(ir);
	ea = reg.r[rb];
	upd = getxo(ir)==311;
	if(ra) {
		ea += reg.r[ra];
		if(upd)
			reg.r[ra] = ea;
		if(trace)
			itrace("%s\tr%d,(r%d+r%d) ea=%lux", ci->name, rd, ra, rb, ea);
	} else {
		if(upd)
			undef(ir);
		if(trace)
			itrace("%s\tr%d,(r%d) ea=%lux", ci->name, rd, rb, ea);
	}

	reg.r[rd] = (short)getmem_h(ea);
}

void
lhbrx(ulong ir)
{
	ulong ea;
	int rb, ra, rd;
	ulong v;

	getarrr(ir);
	ea = reg.r[rb];
	if(ra) {
		ea += reg.r[ra];
		if(trace)
			itrace("%s\tr%d,(r%d+r%d) ea=%lux", ci->name, rd, ra, rb, ea);
	} else {
		if(trace)
			itrace("%s\tr%d,(r%d) ea=%lux", ci->name, rd, rb, ea);
	}
	v = getmem_h(ea);

	reg.r[rd] = ((v&0xFF)<<8)|(v&0xFF);
}

void
sth(ulong ir)
{
	ulong ea;
	int imm, ra, rd, upd, v;

	getairr(ir);
	ea = imm;
	upd = (ir&(1L<<26))!=0;
	if(ra) {
		ea += reg.r[ra];
		if(upd)
			reg.r[ra] = ea;
	} else {
		if(upd)
			undef(ir);
	}
	v = reg.r[rd] & 0xFFFF;
	if(trace)
		itrace("%s\tr%d,%ld(r%d) #%lux=#%lux (%ld)",
					ci->name, rd, imm, ra, ea, v, v);
	putmem_h(ea, v);

}

void
sthx(ulong ir)
{
	ulong ea;
	int ra, rd, upd, rb, v;

	getarrr(ir);
	ea = reg.r[rb];
	upd = getxo(ir)==247;
	v = reg.r[rd] & 0xFFFF;
	if(ra) {
		ea += reg.r[ra];
		if(upd)
			reg.r[ra] = ea;
		if(trace)
			itrace("%s\tr%d,(r%d+r%d) #%lux=#%lux (%ld)",
					ci->name, rd, ra, rb, ea, v, v);
	} else {
		if(upd)
			undef(ir);
		if(trace)
			itrace("%s\tr%d,(r%d) #%lux=#%lux (%ld)",
					ci->name, rd, rb, ea, v, v);
	}
	putmem_h(ea, v);
}

void
sthbrx(ulong ir)
{
	ulong ea;
	int ra, rd, rb;
	ulong v;

	getarrr(ir);
	ea = reg.r[rb];
	v = reg.r[rd];
	v = ((v&0xFF)<<8)|(v&0xFF);
	if(ra) {
		ea += reg.r[ra];
		if(trace)
			itrace("%s\tr%d,(r%d+r%d) #%lux=#%lux (%ld)",
					ci->name, rd, ra, rb, ea, v, v);
	} else {
		if(trace)
			itrace("%s\tr%d,(r%d) #%lux=#%lux (%ld)",
					ci->name, rd, rb, ea, v, v);
	}
	putmem_h(ea, v);
}

void
lwbrx(ulong ir)
{
	ulong ea;
	int rb, ra, rd, i;
	ulong v;

	getarrr(ir);
	if(ir & Rc)
		undef(ir);
	ea = reg.r[rb];
	if(ra) {
		ea += reg.r[ra];
		if(trace)
			itrace("%s\tr%d,(r%d+r%d) ea=%lux", ci->name, rd, ra, rb, ea);
	} else {
		if(trace)
			itrace("%s\tr%d,(r%d) ea=%lux", ci->name, rd, rb, ea);
	}
	v = 0;
	for(i = 0; i < 4; i++)
		v = v>>8 | getmem_b(ea++);	/* assume unaligned load is allowed */
	reg.r[rd] = v;
}

void
stwbrx(ulong ir)
{
	ulong ea;
	int rb, ra, rd, i;
	ulong v;

	getarrr(ir);
	if(ir & Rc)
		undef(ir);
	ea = reg.r[rb];
	if(ra) {
		ea += reg.r[ra];
		if(trace)
			itrace("%s\tr%d,(r%d+r%d) ea=%lux", ci->name, rd, ra, rb, ea);
	} else {
		if(trace)
			itrace("%s\tr%d,(r%d) ea=%lux", ci->name, rd, rb, ea);
	}
	v = 0;
	for(i = 0; i < 4; i++) {
		putmem_b(ea++, v & 0xFF);	/* assume unaligned store is allowed */
		v >>= 8;
	}
}

void
lswi(ulong ir)
{
	ulong ea;
	int rb, ra, rd, n, i, r, b;

	getarrr(ir);
	if(ir & Rc)
		undef(ir);
	n = rb;
	if(n == 0)
		n = 32;
	ea = 0;
	if(ra) {
		ea += reg.r[ra];
		if(trace)
			itrace("%s\tr%d,(r%d),%d ea=%lux", ci->name, rd, ra, n, ea);
	} else {
		if(trace)
			itrace("%s\tr%d,(0),%d ea=0", ci->name, rd, n);
	}
	i = -1;
	r = rd-1;
	while(--n >= 0) {
		if(i < 0) {
			r = (r+1)&0x1F;
			if(ra == 0 || r != ra)
				reg.r[r] = 0;
			i = 24;
		}
		b = getmem_b(ea++);
		if(ra == 0 || r != ra)
			reg.r[r] = (reg.r[r] & ~(0xFF<<i)) | (b << i);
		i -= 8;
	}
}

void
lswx(ulong ir)
{
	ulong ea;
	int rb, ra, rd, n, i, r, b;

	getarrr(ir);
	if(ir & Rc)
		undef(ir);
	n = reg.xer & 0x7F;
	ea = reg.r[rb];
	if(ra) {
		ea += reg.r[ra];
		if(trace)
			itrace("%s\tr%d,(r%d+r%d) ea=%lux n=%d", ci->name, rd, ra, rb, ea, n);
	} else {
		if(trace)
			itrace("%s\tr%d,(r%d) ea=%lux n=%d", ci->name, rd, rb, ea, n);
	}
	i = -1;
	r = rd-1;
	while(--n >= 0) {
		if(i < 0) {
			r = (r+1)&0x1F;
			if((ra == 0 || r != ra) && r != rb)
				reg.r[r] = 0;
			i = 24;
		}
		b = getmem_b(ea++);
		if((ra == 0 || r != ra) && r != rb)
			reg.r[r] = (reg.r[r] & ~(0xFF<<i)) | (b << i);
		i -= 8;
	}
}

void
stswx(ulong ir)
{
	ulong ea;
	int rb, ra, rd, n, i, r;

	getarrr(ir);
	if(ir & Rc)
		undef(ir);
	n = reg.xer & 0x7F;
	ea = reg.r[rb];
	if(ra) {
		ea += reg.r[ra];
		if(trace)
			itrace("%s\tr%d,(r%d+r%d) ea=%lux n=%d", ci->name, rd, ra, rb, ea, n);
	} else {
		if(trace)
			itrace("%s\tr%d,(r%d) ea=%lux n=%d", ci->name, rd, rb, ea, n);
	}
	i = -1;
	r = rd-1;
	while(--n >= 0) {
		if(i < 0) {
			r = (r+1)&0x1F;
			i = 24;
		}
		putmem_b(ea++, (reg.r[r]>>i)&0xFF);
		i -= 8;
	}
}

void
stswi(ulong ir)
{
	ulong ea;
	int rb, ra, rd, n, i, r;

	getarrr(ir);
	if(ir & Rc)
		undef(ir);
	n = rb;
	if(n == 0)
		n = 32;
	ea = 0;
	if(ra) {
		ea += reg.r[ra];
		if(trace)
			itrace("%s\tr%d,(r%d),%d ea=%lux", ci->name, rd, ra, n, ea);
	} else {
		if(trace)
			itrace("%s\tr%d,(0),%d ea=0", ci->name, rd, n);
	}
	i = -1;
	r = rd-1;
	while(--n >= 0) {
		if(i < 0) {
			r = (r+1)&0x1F;
			i = 24;
		}
		putmem_b(ea++, (reg.r[r]>>i)&0xFF);
		i -= 8;
	}
}

void
lmw(ulong ir)
{
	ulong ea;
	int ra, rd, r;
	long imm;

	getairr(ir);
	ea = imm;
	if(ra)
		ea += reg.r[ra];
	if(trace)
		itrace("%s\tr%d,%ld(r%d) ea=%lux", ci->name, rd, imm, ra, ea);

	for(r = rd; r <= 31; r++) {
		if(r != 0 && r != rd)
			reg.r[rd] = getmem_w(ea);
		ea += 4;
	}
}

void
stmw(ulong ir)
{
	ulong ea;
	int ra, rd, r;
	long imm;

	getairr(ir);
	ea = imm;
	if(ra)
		ea += reg.r[ra];
	if(trace)
		itrace("%s\tr%d,%ld(r%d) ea=%lux", ci->name, rd, imm, ra, ea);

	for(r = rd; r <= 31; r++) {
		putmem_w(ea, reg.r[rd]);
		ea += 4;
	}
}

void
twi(ulong ir)
{
	int rd, ra;
	long a, imm;

	getairr(ir);
	a = reg.r[ra];
	if(trace)
		itrace("twi\t#%.2x,r%d,$0x%lux (%ld)", rd, ra, imm, imm);
	if(a < imm && rd&0x10 ||
	   a > imm && rd&0x08 ||
	   a == imm && rd&0x04 ||
	   (ulong)a < imm && rd&0x02 ||
	   (ulong)a > imm && rd&0x01) {
		Bprint(bioout, "program_exception (trap type)\n");
		longjmp(errjmp, 0);
	}
}

void
tw(ulong ir)
{
	int rd, ra, rb;
	long a, b;

	getarrr(ir);
	a = reg.r[ra];
	b = reg.r[rb];
	if(trace)
		itrace("tw\t#%.2x,r%d,r%d", rd, ra, rb);
	if(a < b && rd&0x10 ||
	   a > b && rd&0x08 ||
	   a == b && rd&0x04 ||
	   (ulong)a < b && rd&0x02 ||
	   (ulong)a > b && rd&0x01) {
		Bprint(bioout, "program_exception (trap type)\n");
		longjmp(errjmp, 0);
	}
}

void
sync(ulong ir)
{
	USED(ir);
	if(trace)
		itrace("sync");
}

void
icbi(ulong ir)
{
	int rd, ra, rb;

	if(ir & Rc)
		undef(ir);
	getarrr(ir);
	USED(rd);
	if(trace)
		itrace("%s\tr%d,r%d", ci->name, ra, rb);
}

void
dcbf(ulong ir)
{
	int rd, ra, rb;

	if(ir & Rc)
		undef(ir);
	getarrr(ir);
	USED(rd);
	if(trace)
		itrace("%s\tr%d,r%d", ci->name, ra, rb);
}

void
dcbst(ulong ir)
{
	int rd, ra, rb;

	if(ir & Rc)
		undef(ir);
	getarrr(ir);
	USED(rd);
	if(trace)
		itrace("%s\tr%d,r%d", ci->name, ra, rb);
}

void
dcbt(ulong ir)
{
	int rd, ra, rb;

	if(ir & Rc)
		undef(ir);
	getarrr(ir);
	USED(rd);
	if(trace)
		itrace("%s\tr%d,r%d", ci->name, ra, rb);
}

void
dcbtst(ulong ir)
{
	int rd, ra, rb;

	if(ir & Rc)
		undef(ir);
	getarrr(ir);
	USED(rd);
	if(trace)
		itrace("%s\tr%d,r%d", ci->name, ra, rb);
}

void
dcbz(ulong ir)
{
	int rd, ra, rb;

	if(ir & Rc)
		undef(ir);
	getarrr(ir);
	USED(rd);
	if(trace)
		itrace("%s\tr%d,r%d", ci->name, ra, rb);
}