iu.c

这是一个同样来自贝尔实验室的和UNIX有着渊源的操作系统, 其简洁的设计和实现易于我们学习和理解

		reg.xer &= ~XER_OV;
		if(v>>1)
			reg.xer |= XER_SO | XER_OV;
	}
	reg.r[rd] = (ulong)r;
	if(ir & Rc)
		setcr(0, reg.r[rd]);
	if(trace)
		itrace("%s%s%s\tr%d,r%d", ci->name, ir&OE?"o":"", ir&1?".":"", rd, ra);
}

void
divw(ulong ir)
{
	int rd, ra, rb;

	getarrr(ir);
	if(reg.r[rb] != 0 && ((ulong)reg.r[ra] != 0x80000000 || reg.r[rb] != -1))
		reg.r[rd] = reg.r[ra]/reg.r[rb];
	else if(ir & OE)
		reg.xer |= XER_SO | XER_OV;
	if(ir & Rc)
		setcr(0, reg.r[rd]);
	if(trace)
		itrace("%s%s%s\tr%d,r%d,r%d", ci->name, ir&OE?"o":"", ir&1?".":"", rd, ra, rb);
}

void
divwu(ulong ir)
{
	int rd, ra, rb;

	getarrr(ir);
	if(reg.r[rb] != 0)
		reg.r[rd] = (ulong)reg.r[ra]/(ulong)reg.r[rb];
	else if(ir & OE)
		reg.xer |= XER_SO | XER_OV;
	if(ir & Rc)
		setcr(0, reg.r[rd]);
	if(trace)
		itrace("%s%s%s\tr%d,r%d,r%d", ci->name, ir&OE?"o":"", ir&1?".":"", rd, ra, rb);
}

void
mcrxr(ulong ir)
{
	int rd, ra, rb;

	getarrr(ir);
	if(rd & 3 || ra != 0 || rb != 0 || ir & Rc)
		undef(ir);
	rd >>= 2;
	reg.cr = (reg.cr & ~mkCR(rd, 0xF)) | mkCR(rd, reg.xer>>28);
	reg.xer &= ~(0xF<<28);
}

void
mtcrf(ulong ir)
{
	int rs, crm, i;
	ulong m;

	if(ir & ((1<<20)|(1<<11)|Rc))
		undef(ir);
	rs = (ir>>21)&0x1F;
	crm = (ir>>12)&0xFF;
	m = 0;
	for(i = 0x80; i; i >>= 1) {
		m <<= 4;
		if(crm & i)
			m |= 0xF;
	}
	reg.cr = (reg.cr & ~m) | (reg.r[rs] & m);
}

void
mfcr(ulong ir)
{
	int rd, ra, rb;

	getarrr(ir);
	if(ra != 0 || rb != 0 || ir & Rc)
		undef(ir);
	reg.r[rd] = reg.cr;
}

void
mulhw(ulong ir)
{
	int rd, ra, rb;

	getarrr(ir);
	reg.r[rd] = ((vlong)(long)reg.r[ra]*(long)reg.r[rb])>>32;
	if(ir & Rc)
		setcr(0, reg.r[rd]);
	if(trace)
		itrace("%s%s%s\tr%d,r%d,r%d", ci->name, ir&OE?"o":"", ir&Rc?".":"", rd, ra, rb);
	/* BUG: doesn't set OV */
}

void
mulhwu(ulong ir)
{
	int rd, ra, rb;

	getarrr(ir);
	reg.r[rd] = ((uvlong)(ulong)reg.r[ra]*(ulong)reg.r[rb])>>32;
	if(ir & Rc)
		setcr(0, reg.r[rd]);	/* not sure whether CR setting is signed or unsigned */
	if(trace)
		itrace("%s%s%s\tr%d,r%d,r%d", ci->name, ir&OE?"o":"", ir&Rc?".":"", rd, ra, rb);
	/* BUG: doesn't set OV */
}

void
mullw(ulong ir)
{
	int rd, ra, rb;

	getarrr(ir);
	reg.r[rd] = (uvlong)(ulong)reg.r[ra]*(ulong)reg.r[rb];
	if(ir & Rc)
		setcr(0, reg.r[rd]);
	if(trace)
		itrace("%s%s%s\tr%d,r%d,r%d", ci->name, ir&OE?"o":"", ir&Rc?".":"", rd, ra, rb);
	/* BUG: doesn't set OV */
}

void
mulli(ulong ir)
{
	int rd, ra;
	long imm;

	getairr(ir);
	reg.r[rd] = (uvlong)(ulong)reg.r[ra]*(ulong)imm;
	if(trace)
		itrace("%s\tr%d,r%d,$%ld", ci->name, rd, ra, imm);
}

void
nand(ulong ir)
{
	int rs, ra, rb;

	getlrrr(ir);
	reg.r[ra] = ~(reg.r[rs] & reg.r[rb]);
	if(ir & Rc)
		setcr(0, reg.r[ra]);
	if(trace)
		itrace("%s%s\tr%d,r%d,r%d", ci->name, ir&1?".":"", ra, rs, rb);
}

void
neg(ulong ir)
{
	int rd, ra, rb;

	getarrr(ir);
	if(rb)
		undef(ir);
	if(ir & OE)
		reg.xer &= ~XER_OV;
	if((ulong)reg.r[ra] == 0x80000000) {
		if(ir & OE)
			reg.xer |= XER_SO | XER_OV;
		reg.r[rd] = reg.r[ra];
	} else
		reg.r[rd] = -reg.r[ra];
	if(ir & Rc)
		setcr(0, reg.r[rd]);
}

void
nor(ulong ir)
{
	int rs, ra, rb;

	getlrrr(ir);
	reg.r[ra] = ~(reg.r[rs] | reg.r[rb]);
	if(ir & Rc)
		setcr(0, reg.r[ra]);
	if(trace)
		itrace("%s%s\tr%d,r%d,r%d", ci->name, ir&1?".":"", ra, rs, rb);
}

void
or(ulong ir)
{
	int rs, ra, rb;

	getlrrr(ir);
	reg.r[ra] = reg.r[rs] | reg.r[rb];
	if(ir & Rc)
		setcr(0, reg.r[ra]);
	if(trace) {
		if(rs == rb)
			itrace("mr%s\tr%d,r%d", ir&1?".":"", ra, rs);
		else
			itrace("%s%s\tr%d,r%d,r%d", ci->name, ir&1?".":"", ra, rs, rb);
	}
}

void
orc(ulong ir)
{
	int rs, ra, rb;

	getlrrr(ir);
	reg.r[ra] = reg.r[rs] | ~reg.r[rb];
	if(ir & Rc)
		setcr(0, reg.r[ra]);
	if(trace)
		itrace("%s%s\tr%d,r%d,r%d", ci->name, ir&1?".":"", ra, rs, rb);
}

void
ori(ulong ir)
{
	int rs, ra;
	ulong imm;

	getlirr(ir);
	reg.r[ra] = reg.r[rs] | imm;
	if(trace)
		itrace("%s\tr%d,r%d,$0x%lx", ci->name, ra, rs, imm);
}

void
oris(ulong ir)
{
	int rs, ra;
	ulong imm;

	getlirr(ir);
	reg.r[ra] = reg.r[rs] | (imm<<16);
	if(trace)
		itrace("%s\tr%d,r%d,$0x%lx", ci->name, ra, rs, imm);
}

static ulong
mkmask(int mb, int me)
{
	int i;
	ulong v;

	if(mb > me)
		return mkmask(0, me) | mkmask(mb, 31);
	v = 0;
	for(i=mb; i<=me; i++)
		v |= 1L << (31-i);	/* don't need a loop, but i'm lazy */
	return v;
}

static ulong
rotl(ulong v, int sh)
{
	if(sh == 0)
		return v;
	return (v<<sh) | (v>>(32-sh));
}

void
rlwimi(ulong ir)
{
	int rs, ra, rb, sh;
	ulong m;

	getlrrr(ir);
	sh = rb;
	m = mkmask((ir>>6)&0x1F, (ir>>1)&0x1F);
	reg.r[ra] = (reg.r[ra] & ~m) | (rotl(reg.r[rs], sh) & m);
	if(trace)
		itrace("%s\tr%d,r%d,%d,#%lux", ci->name, ra, rs, sh, m);
	if(ir & 1)
		setcr(0, reg.r[ra]);
}

void
rlwinm(ulong ir)
{
	int rs, ra, rb, sh;
	ulong m;

	getlrrr(ir);
	sh = rb;
	m = mkmask((ir>>6)&0x1F, (ir>>1)&0x1F);
	reg.r[ra] = rotl(reg.r[rs], sh) & m;
	if(trace)
		itrace("%s%s\tr%d,r%d,%d,#%lux", ci->name, ir&Rc?".":"", ra, rs, sh, m);
	if(ir & Rc)
		setcr(0, reg.r[ra]);
}

void
rlwnm(ulong ir)
{
	int rs, ra, rb, sh;
	ulong m;

	getlrrr(ir);
	sh = reg.r[rb] & 0x1F;
	m = mkmask((ir>>6)&0x1F, (ir>>1)&0x1F);
	reg.r[ra] = rotl(reg.r[rs], sh) & m;
	if(trace)
		itrace("%s\tr%d,r%d,r%d,#%lux", ci->name, ra, rs, rb, m);
	if(ir & 1)
		setcr(0, reg.r[ra]);
}

void
slw(ulong ir)
{
	int rs, ra, rb;
	long v;

	getlrrr(ir);
	v = reg.r[rb];
	if((v & 0x20) == 0) {
		v &= 0x1F;
		reg.r[ra] = (ulong)reg.r[rs] << v;
	} else
		reg.r[ra] = 0;
	if(ir & Rc)
		setcr(0, reg.r[ra]);
	if(trace)
		itrace("%s%s\tr%d,r%d,r%d", ci->name, ir&1?".":"", ra, rs, rb);
}

void
sraw(ulong ir)
{
	int rs, ra, rb;
	long v;

	getlrrr(ir);
	v = reg.r[rb];
	if((v & 0x20) == 0) {
		v &= 0x1F;
		if(reg.r[rs]&SIGNBIT && v)
			reg.r[ra] = reg.r[rs]>>v | ~((1<<(32-v))-1);
		else
			reg.r[ra] = reg.r[rs]>>v;
	} else
		reg.r[ra] = reg.r[rs]&SIGNBIT? ~0: 0;
	if(ir & Rc)
		setcr(0, reg.r[ra]);
	if(trace)
		itrace("%s%s\tr%d,r%d,r%d", ci->name, ir&1?".":"", ra, rs, rb);
}

void
srawi(ulong ir)
{
	int rs, ra, rb;
	long v;

	getlrrr(ir);
	v = rb;
	if((v & 0x20) == 0) {
		v &= 0x1F;
		if(reg.r[rs]&SIGNBIT && v)
			reg.r[ra] = reg.r[rs]>>v | ~((1<<(32-v))-1);
		else
			reg.r[ra] = reg.r[rs]>>v;
	} else
		reg.r[ra] = reg.r[rs]&SIGNBIT? ~0: 0;
	if(ir & Rc)
		setcr(0, reg.r[ra]);
	if(trace)
		itrace("%s%s\tr%d,r%d,$%d", ci->name, ir&1?".":"", ra, rs, v);
}

void
srw(ulong ir)
{
	int rs, ra, rb;
	long v;

	getlrrr(ir);
	v = reg.r[rb];
	if((v & 0x20) == 0)
		reg.r[ra] = (ulong)reg.r[rs] >> (v&0x1F);
	else
		reg.r[ra] = 0;
	if(ir & Rc)
		setcr(0, reg.r[ra]);
	if(trace)
		itrace("%s%s\tr%d,r%d,r%d", ci->name, ir&1?".":"", ra, rs, rb);
}

void
subf(ulong ir)
{
	int rd, ra, rb;
	uvlong r;

	getarrr(ir);
	r = (uvlong)((ulong)~reg.r[ra]) + reg.r[rb] + 1;
	if(ir & OE) {
		reg.xer &= ~XER_OV;
		if(r >> 16)
			reg.xer |= XER_SO | XER_OV;
	}
	reg.r[rd] = (ulong)r;
	if(ir & Rc)
		setcr(0, reg.r[rd]);
	if(trace)
		itrace("%s%s%s\tr%d,r%d,r%d", ci->name, ir&OE?"o":"", ir&1?".":"", rd, ra, rb);
}

void
subfc(ulong ir)
{
	int rd, ra, rb;
	ulong v;
	uvlong r;

	getarrr(ir);
	r = (uvlong)((ulong)~reg.r[ra]) + reg.r[rb] + 1;
	v = r>>32;
	reg.xer &= ~XER_CA;
	if(v)
		reg.xer |= XER_CA;
	if(ir & OE) {
		reg.xer &= ~XER_OV;
		if(v>>1)
			reg.xer |= XER_SO | XER_OV;
	}
	reg.r[rd] = (ulong)r;
	if(ir & Rc)
		setcr(0, reg.r[rd]);
	if(trace)
		itrace("%s%s%s\tr%d,r%d,r%d", ci->name, ir&OE?"o":"", ir&1?".":"", rd, ra, rb);
}

void
subfe(ulong ir)
{
	int rd, ra, rb;
	ulong v;
	uvlong r;

	getarrr(ir);
	r = (uvlong)((ulong)~reg.r[ra]) + reg.r[rb] + (reg.xer&XER_CA)!=0;
	v = r>>32;
	reg.xer &= ~XER_CA;
	if(v)
		reg.xer |= XER_CA;
	if(ir & OE) {
		reg.xer &= ~XER_OV;
		if(v>>1)
			reg.xer |= XER_SO | XER_OV;
	}
	reg.r[rd] = (ulong)r;
	if(ir & Rc)
		setcr(0, reg.r[rd]);
	if(trace)
		itrace("%s%s%s\tr%d,r%d,r%d", ci->name, ir&OE?"o":"", ir&1?".":"", rd, ra, rb);
}

void
subfic(ulong ir)
{
	int rd, ra;
	long imm;
	ulong v;
	uvlong r;

	getairr(ir);
	r = (uvlong)((ulong)~reg.r[ra]) + imm + 1;
	v = r>>32;
	reg.xer &= ~XER_CA;
	if(v)
		reg.xer |= XER_CA;
	reg.r[rd] = (ulong)r;
	if(trace)
		itrace("%s\tr%d,r%d,$%ld", ci->name, rd, ra, imm);
}

void
subfme(ulong ir)
{
	int rd, ra, rb;
	ulong v;
	uvlong r;

	getarrr(ir);
	if(rb)
		undef(ir);
	r = (uvlong)((ulong)~reg.r[ra]) + 0xFFFFFFFF + (reg.xer&XER_CA)!=0;
	v = r>>32;
	reg.xer &= ~XER_CA;
	if(v)
		reg.xer |= XER_CA;
	if(ir & OE) {
		reg.xer &= ~XER_OV;
		if(v>>1)
			reg.xer |= XER_SO | XER_OV;
	}
	reg.r[rd] = (ulong)r;
	if(ir & Rc)
		setcr(0, reg.r[rd]);
	if(trace)
		itrace("%s%s%s\tr%d,r%d", ci->name, ir&OE?"o":"", ir&1?".":"", rd, ra);
}

void
subfze(ulong ir)
{
	int rd, ra, rb;
	ulong v;
	uvlong r;

	getarrr(ir);
	if(rb)
		undef(ir);
	r = (uvlong)((ulong)~reg.r[ra]) + (reg.xer&XER_CA)!=0;
	v = r>>32;
	reg.xer &= ~XER_CA;
	if(v)
		reg.xer |= XER_CA;
	if(ir & OE) {
		reg.xer &= ~XER_OV;
		if(v>>1)
			reg.xer |= XER_SO | XER_OV;
	}
	reg.r[rd] = (ulong)r;
	if(ir & Rc)
		setcr(0, reg.r[rd]);
	if(trace)
		itrace("%s%s%s\tr%d,r%d", ci->name, ir&OE?"o":"", ir&1?".":"", rd, ra);
}

void
xor(ulong ir)
{
	int rs, ra, rb;

	getlrrr(ir);
	reg.r[ra] = reg.r[rs] ^ reg.r[rb];
	if(trace)
		itrace("%s\tr%d,r%d,r%d", ci->name, ra, rs, rb);
}

void
xori(ulong ir)
{
	int rs, ra;
	ulong imm;

	getlirr(ir);
	reg.r[ra] = reg.r[rs] ^ imm;
	if(trace)
		itrace("%s\tr%d,r%d,$0x%lx", ci->name, ra, rs, imm);
}

void
xoris(ulong ir)
{
	int rs, ra;
	ulong imm;

	getlirr(ir);
	reg.r[ra] = reg.r[rs] ^ (imm<<16);
	if(trace)
		itrace("%s\tr%d,r%d,$0x%lx", ci->name, ra, rs, imm);
}

void
lwz(ulong ir)
{
	ulong ea;
	int ra, rd, upd;
	long imm;

	getairr(ir);
	ea = imm;
	upd = (ir&(1L<<26))!=0;
	if(ra) {
		ea += reg.r[ra];
		if(upd)
			reg.r[ra] = ea;
	} else {
		if(upd)
			undef(ir);
	}
	if(trace)
		itrace("%s\tr%d,%ld(r%d) ea=%lux", ci->name, rd, imm, ra, ea);

	reg.r[rd] = getmem_w(ea);
}

void
lwzx(ulong ir)
{
	ulong ea;
	int rb, ra, rd, upd;

	getarrr(ir);
	ea = reg.r[rb];
	upd = getxo(ir)==55;
	if(ra) {
		ea += reg.r[ra];
		if(upd)
			reg.r[ra] = ea;
		if(trace)
			itrace("%s\tr%d,(r%d+r%d) ea=%lux", ci->name, rd, ra, rb, ea);
	} else {
		if(upd)
			undef(ir);
		if(trace)
			itrace("%s\tr%d,(r%d) ea=%lux", ci->name, rd, rb, ea);
	}

	reg.r[rd] = getmem_w(ea);
}

void
lwarx(ulong ir)
{
	lwzx(ir);
}

void
lbz(ulong ir)
{
	ulong ea;
	int ra, rd, upd;
	long imm;

	getairr(ir);
	ea = imm;
	upd = (ir&(1L<<26))!=0;
	if(ra) {
		ea += reg.r[ra];
		if(upd)
			reg.r[ra] = ea;
	} else {
		if(upd)
			undef(ir);
	}
	if(trace)
		itrace("%s\tr%d,%ld(r%d) ea=%lux", ci->name, rd, imm, ra, ea);

	reg.r[rd] = getmem_b(ea);
}

void
lbzx(ulong ir)
{
	ulong ea;
	int rb, ra, rd, upd;

	getarrr(ir);
	ea = reg.r[rb];
	upd = getxo(ir)==119;
	if(ra) {
		ea += reg.r[ra];
		if(upd)
			reg.r[ra] = ea;
		if(trace)
			itrace("%s\tr%d,(r%d+r%d) ea=%lux", ci->name, rd, ra, rb, ea);
	} else {
		if(upd)
			undef(ir);
		if(trace)
			itrace("%s\tr%d,(r%d) ea=%lux", ci->name, rd, rb, ea);
	}

	reg.r[rd] = getmem_b(ea);
}

void
stw(ulong ir)
{