run.c

这是一个同样来自贝尔实验室的和UNIX有着渊源的操作系统, 其简洁的设计和实现易于我们学习和理解

		itrace("%s%s\tR%d%s%d,R%d,R%d =#%x",
			reg.ip->name, cond[reg.cond], rm, shtype[st], sc, rn, rd,
			reg.r[rd]);
	if(rd == REGPC)
		reg.r[rd] -= 4;
}

/*
 * data processing instruction (R<>R),R,R
 */
void
Idp2(ulong inst)
{
	int rn, rd, rm, rs, st;
	long o1, o2, o3;

	rn = (inst>>16) & 0xf;
	rd = (inst>>12) & 0xf;
	rm = inst & 0xf;
	st = (inst>>5) & 0x3;
	rs = (inst>>8) & 0xf;
	o1 = reg.r[rn];
	if(rn == REGPC)
		o1 += 8;
	o2 = reg.r[rm];
	if(rm == REGPC)
		o2 += 8;
	o3 = reg.r[rs];
	if(rs == REGPC)
		o3 += 8;
	o2 = shift(o2, st, o3, 1);
	dpex(inst, o1, o2, rd);
	if(trace)
		itrace("%s%s\tR%d%sR%d=%d,R%d,R%d =#%x",
			reg.ip->name, cond[reg.cond], rm, shtype[st], rs, o3, rn, rd,
			reg.r[rd]);
	if(rd == REGPC)
		reg.r[rd] -= 4;
}

/*
 * data processing instruction #<>#,R,R
 */
void
Idp3(ulong inst)
{
	int rn, rd, sc;
	long o1, o2;

	rn = (inst>>16) & 0xf;
	rd = (inst>>12) & 0xf;
	o1 = reg.r[rn];
	if(rn == REGPC)
		o1 += 8;
	o2 = inst & 0xff;
	sc = (inst>>7) & 0x1e;
	o2 = (o2 >> sc) | (o2 << (32 - sc));

	dpex(inst, o1, o2, rd);
	if(trace)
		itrace("%s%s\t#%x,R%d,R%d =#%x",
			reg.ip->name, cond[reg.cond], o2, rn, rd,
			reg.r[rd]);
	if(rd == REGPC)
		reg.r[rd] -= 4;
}

void
Imul(ulong inst)
{
	int rs, rd, rm;

	rd = (inst>>16) & 0xf;
	rs = (inst>>8) & 0xf;
	rm = inst & 0xf;

	if(rd == REGPC || rs == REGPC || rm == REGPC || rd == rm)
		undef(inst);

	reg.r[rd] = reg.r[rm]*reg.r[rs];

	if(trace)
		itrace("%s%s\tR%d,R%d,R%d =#%x",
			reg.ip->name, cond[reg.cond], rs, rm, rd,
			reg.r[rd]);
}

void
Imull(ulong inst)
{
	vlong v;
	int rs, rd, rm, rn;

	rd = (inst>>16) & 0xf;
	rn = (inst>>12) & 0xf;
	rs = (inst>>8) & 0xf;
	rm = inst & 0xf;

	if(rd == REGPC || rn == REGPC || rs == REGPC || rm == REGPC
	|| rd == rm || rn == rm || rd == rn)
		undef(inst);

	if(inst & (1<<22)){
		v = (vlong)reg.r[rm] * (vlong)reg.r[rs];
		if(inst & (1 << 21))
			v += reg.r[rn];
	}else{
		v = (uvlong)(ulong)reg.r[rm] * (uvlong)(ulong)reg.r[rs];
		if(inst & (1 << 21))
			v += (ulong)reg.r[rn];
	}
	reg.r[rd] = v >> 32;
	reg.r[rn] = v;

	if(trace)
		itrace("%s%s\tR%d,R%d,(R%d,R%d) =#%llx",
			reg.ip->name, cond[reg.cond], rs, rm, rn, rd,
			v);
}

void
Imula(ulong inst)
{
	int rs, rd, rm, rn;

	rd = (inst>>16) & 0xf;
	rn = (inst>>12) & 0xf;
	rs = (inst>>8) & 0xf;
	rm = inst & 0xf;

	if(rd == REGPC || rn == REGPC || rs == REGPC || rm == REGPC || rd == rm)
		undef(inst);

	reg.r[rd] = reg.r[rm]*reg.r[rs] + reg.r[rn];

	if(trace)
		itrace("%s%s\tR%d,R%d,R%d,R%d =#%x",
			reg.ip->name, cond[reg.cond], rs, rm, rn, rd,
			reg.r[rd]);
}

void
Iswap(ulong inst)
{
	int rn, rd, rm;
	ulong address, value, bbit;

	bbit = inst & (1<<22);
	rn = (inst>>16) & 0xf;
	rd = (inst>>12) & 0xf;
	rm = (inst>>0) & 0xf;

	address = reg.r[rn];
	if(bbit) {
		value = getmem_b(address);
		putmem_b(address, reg.r[rm]);
	} else {
		value = getmem_w(address);
		putmem_w(address, reg.r[rm]);
	}
	reg.r[rd] = value;

	if(trace) {
		char *bw, *dotc;

		bw = "";
		if(bbit)
			bw = "B";
		dotc = cond[reg.cond];

		itrace("SWP%s%s\t#%x(R%d),R%d #%lux=#%x",
			bw, dotc,
			rn, rd,
			address, value);
	}
}

/*
 * load/store word/byte
 */
void
Imem1(ulong inst)
{
	int rn, rd, off, rm, sc, st;
	ulong address, value, pbit, ubit, bbit, wbit, lbit, bit25;

	bit25 = inst & (1<<25);
	pbit = inst & (1<<24);
	ubit = inst & (1<<23);
	bbit = inst & (1<<22);
	wbit = inst & (1<<21);
	lbit = inst & (1<<20);
	rn = (inst>>16) & 0xf;
	rd = (inst>>12) & 0xf;

	SET(st);
	SET(sc);
	SET(rm);
	if(bit25) {
		rm = inst & 0xf;
		st = (inst>>5) & 0x3;
		sc = (inst>>7) & 0x1f;
		off = reg.r[rm];
		if(rm == REGPC)
			off += 8;
		off = shift(off, st, sc, 0);
	} else {
		off = inst & 0xfff;
	}
	if(!ubit)
		off = -off;
	if(rn == REGPC)
		off += 8;

	address = reg.r[rn];
	if(pbit)
		address += off;

	if(lbit) {
		if(bbit)
			value = getmem_b(address);
		else
			value = getmem_w(address);
		if(rd == REGPC)
			value -= 4;
		reg.r[rd] = value;
	} else {
		value = reg.r[rd];
		if(rd == REGPC)
			value -= 4;
		if(bbit)
			putmem_b(address, value);
		else
			putmem_w(address, value);
	}
	if(!(pbit && !wbit))
		reg.r[rn] += off;

	if(trace) {
		char *bw, *dotp, *dotc;

		bw = "W";
		if(bbit)
			bw = "BU";
		dotp = "";
		if(!pbit)
			dotp = ".P";
		dotc = cond[reg.cond];

		if(lbit) {
			if(!bit25)
				itrace("MOV%s%s%s\t#%x(R%d),R%d #%lux=#%x",
					bw, dotp, dotc,
					off, rn, rd,
					address, value);
			else
				itrace("MOV%s%s%s\t(R%d%s%d)(R%d),R%d  #%lux=#%x",
					bw, dotp, dotc,
					rm, shtype[st], sc, rn, rd,
					address, value);
		} else {
			if(!bit25)
				itrace("MOV%s%s%s\tR%d,#%x(R%d) #%lux=#%x",
					bw, dotp, dotc,
					rd, off, rn,
					address, value);
			else
				itrace("MOV%s%s%s\tR%d,(R%d%s%d)(R%d) #%lux=#%x",
					bw, dotp, dotc,
					rd, rm, shtype[st], sc, rn,
					address, value);
		}
	}
}

/*
 * load/store unsigned byte/half word
 */
void
Imem2(ulong inst)
{
	int rn, rd, off, rm;
	ulong address, value, pbit, ubit, hbit, sbit, wbit, lbit, bit22;

	pbit = inst & (1<<24);
	ubit = inst & (1<<23);
	bit22 = inst & (1<<22);
	wbit = inst & (1<<21);
	lbit = inst & (1<<20);
	sbit = inst & (1<<6);
	hbit = inst & (1<<5);
	rn = (inst>>16) & 0xf;
	rd = (inst>>12) & 0xf;

	SET(rm);
	if(bit22) {
		off = ((inst>>4) & 0xf0) | (inst & 0xf);
	} else {
		rm = inst & 0xf;
		off = reg.r[rm];
		if(rm == REGPC)
			off += 8;
	}
	if(!ubit)
		off = -off;
	if(rn == REGPC)
		off += 8;

	address = reg.r[rn];
	if(pbit)
		address += off;

	if(lbit) {
		if(hbit) {
			value = getmem_h(address);
			if(sbit && (value & 0x8000))
				value |= 0xffff0000;
		} else {
			value = getmem_b(address);
			if(value & 0x80)
				value |= 0xffffff00;
		}
		if(rd == REGPC)
			value -= 4;
		reg.r[rd] = value;
	} else {
		value = reg.r[rd];
		if(rd == REGPC)
			value -= 4;
		if(hbit) {
			putmem_h(address, value);
		} else {
			putmem_b(address, value);
		}
	}
	if(!(pbit && !wbit))
		reg.r[rn] += off;

	if(trace) {
		char *hb, *dotp, *dotc;

		hb = "B";
		if(hbit)
			hb = "H";
		dotp = "";
		if(!pbit)
			dotp = ".P";
		dotc = cond[reg.cond];

		if(lbit) {
			if(bit22)
				itrace("MOV%s%s%s\t#%x(R%d),R%d #%lux=#%x",
					hb, dotp, dotc,
					off, rn, rd,
					address, value);
			else
				itrace("MOV%s%s%s\t(R%d)(R%d),R%d  #%lux=#%x",
					hb, dotp, dotc,
					rm, rn, rd,
					address, value);
		} else {
			if(bit22)
				itrace("MOV%s%s%s\tR%d,#%x(R%d) #%lux=#%x",
					hb, dotp, dotc,
					rd, off, rn,
					address, value);
			else
				itrace("MOV%s%s%s\tR%d,(R%d)(R%d) #%lux=#%x",
					hb, dotp, dotc,
					rd, rm, rn,
					address, value);
		}
	}
}

void
Ilsm(ulong inst)
{
	char pbit, ubit, sbit, wbit, lbit;
	int i, rn, reglist;
	ulong address, predelta, postdelta;

	pbit = (inst>>24) & 0x1;
	ubit = (inst>>23) & 0x1;
	sbit = (inst>>22) & 0x1;
	wbit = (inst>>21) & 0x1;
	lbit = (inst>>20) & 0x1;
	rn =   (inst>>16) & 0xf;
	reglist = inst & 0xffff;

	if(reglist & 0x8000)
		undef(reg.ir);
	if(sbit)
		undef(reg.ir);

	address = reg.r[rn];

	if(pbit) {
		predelta = 4;
		postdelta = 0;
	} else {
		predelta = 0;
		postdelta = 4;
	}
	if(ubit) {
		for (i = 0; i < 16; ++i) {
			if(!(reglist & (1 << i)))
				continue;
			address += predelta;
			if(lbit)
				reg.r[i] = getmem_w(address);
			else
				putmem_w(address, reg.r[i]);
			address += postdelta;
		}
	} else {
		for (i = 15; 0 <= i; --i) {
			if(!(reglist & (1 << i)))
				continue;
			address -= predelta;
			if(lbit)
				reg.r[i] = getmem_w(address);
			else
				putmem_w(address, reg.r[i]);
			address -= postdelta;
		}
	}
	if(wbit) {
		reg.r[rn] = address;
	}

	if(trace) {
		itrace("%s.%c%c\tR%d=%lux%s, <%lux>",
			(lbit ? "LDM" : "STM"), (ubit ? 'I' : 'D'), (pbit ? 'B' : 'A'),
			rn, reg.r[rn], (wbit ? "!" : ""), reglist);
	}
}

void
Ib(ulong inst)
{
	long v;

	v = inst & 0xffffff;
	v = reg.r[REGPC] + 8 + ((v << 8) >> 6);
	if(trace)
		itrace("B%s\t#%lux", cond[reg.cond], v);
	reg.r[REGPC] = v - 4;
}

void
Ibl(ulong inst)
{
	long v;
	Symbol s;

	v = inst & 0xffffff;
	v = reg.r[REGPC] + 8 + ((v << 8) >> 6);
	if(trace)
		itrace("BL%s\t#%lux", cond[reg.cond], v);

	if(calltree) {
		findsym(v, CTEXT, &s);
		Bprint(bioout, "%8lux %s(", reg.r[REGPC], s.name);
		printparams(&s, reg.r[13]);
		Bprint(bioout, "from ");
		printsource(reg.r[REGPC]);
		Bputc(bioout, '\n');
	}

	reg.r[REGLINK] = reg.r[REGPC] + 4;
	reg.r[REGPC] = v - 4;
}