virge.c

这是一个同样来自贝尔实验室的和UNIX有着渊源的操作系统, 其简洁的设计和实现易于我们学习和理解

				vga->crt[0x67] |= 0x70;
			else
				vga->crt[0x67] |= 0xD0;
			break;
		case 32:
			/*
			 * The ViRGE and ViRGE/VX manuals make no mention of
			 * 32-bit mode (which the GX/2 calls 24-bit unpacked mode).
			 */
			if(id != 0x8A10)
				error("32-bit mode only supported on the GX/2");
			vga->crt[0x67] |= 0xD0;
			break;
		}

		/*
		 * Set new MMIO method
		 */
		vga->crt[0x53] &= ~0x18;
		vga->crt[0x53] |= 0x08;

		break;

	case 0x8C2E:				/* SuperSavage/IXC16 (let's try this -rsc) */
	case 0x8C10:				/* Savage MX/MV */
	case 0x8C12:				/* Savage4/IX-MV */
		/*
		 * Experience shows the -1 (according to the manual)
		 * is incorrect.
		 */
		x = width/8 /*-1*/;
		vga->crt[0x91] = x;
		vga->crt[0x90] &= ~0x07;
		vga->crt[0x90] |= (x>>8) & 0x07;

	case 0x8D04:				/* ProSavage DDR, K.Okamoto */
		x = mode->x * ((mode->z + 7) / 8);
		x = (x + 7) / 8;
		vga->crt[0x91] = x & 0xFF;
		vga->crt[0x90] = (x >> 8) | 0x80;

		/*FALLTHROUGH*/

	case 0x8A22:				/* Savage4 */
	case 0x8A25:				/* ProSavage PN133 */
	case 0x8A26:				/* ProSavage KN133 */
		/*
		 * The Savage 4 is frustratingly similar to the
		 * ViRGE/GX2, but has enough slight differences
		 * to warrant special treatment.  Blog.
		 */
		vga->crt[0x66] = 0x89;
		vga->crt[0x67] = 0;
		vga->crt[0x85] = 0x02;
		vga->crt[0x31] |= 0x08;

		vga->crt[0x13] = (width>>3) & 0xFF;
		vga->crt[0x51] &= ~0x30;
		vga->crt[0x51] |= (width>>7) & 0x30;

		/* pull screen width from GBD for graphics engine. */
		vga->crt[0x50] = 0xC1;	/* set color mode */

		/*
		 * The high nibble is the mode; or'ing in 0x02 turns
		 * on support for gamma correction via the DACs, but I
		 * haven't figured out how to turn on the 8-bit DACs,
		 * so gamma correction stays off.
		 */
		switch(vga->mode->z){
		default:
			error("%d-bit mode not supported on savage 4\n", vga->mode->z);
		case 8:
			vga->crt[0x67] |= 0x00;
			vga->crt[0x50] |= 0<<4;
			break;
		case 15:
			vga->crt[0x67] |= 0x20;
			vga->crt[0x50] |= 1<<4;
			break;
		case 16:
			vga->crt[0x67] |= 0x40;
			vga->crt[0x50] |= 1<<4;
			/*
			 * Manual says this should be accompanied by setting
			 * the clock-doubled modes but this seems to be the
			 * right answer.
			 * Should check if using doubled modes tidies any of
			 * this up.
			 */
			if(id == 0x8C12 || id == 0x8C2E || id == 0x8C10)
				vga->crt[0x67] |= 0x10;
			break;
		case 32:
			vga->crt[0x67] |= 0xD0;
			vga->crt[0x50] |= 3<<4;
			break;
		}
		break;
	}

	/*
	 * Clock bits. If the desired video clock is
	 * one of the two standard VGA clocks it can just be
	 * set using bits <3:2> of vga->misc, otherwise we
	 * need to programme the DCLK PLL.
	 */
	if(val = dbattr(vga->mode->attr, "noclockset")){
		 if((noclockset = strtol(val, &p, 0)) == 0 && p == val)
			error("%s: invalid 'noclockset' attr\n", ctlr->name);
	}
	if(vga->f[0] == 0)
		vga->f[0] = vga->mode->frequency;
	vga->misc &= ~0x0C;
	if(vga->f[0] == VgaFreq0){
		/* nothing to do */;
	}
	else if(vga->f[0] == VgaFreq1)
		vga->misc |= 0x04;
	else if(noclockset){
		/*
		 * Don't touch the clock on the Aurora64V+
		 * and optionally on some others.
		 */
		vga->misc |= 0x0C;
	}
	else{
		if(vga->f[0] > pclk)
			error("%s: invalid pclk - %lud\n",
				ctlr->name, vga->f[0]);

		trio64clock(vga, ctlr);
		switch(id){

		case 0x8A10:			/* ViRGE/GX2 */
			vga->sequencer[0x12] = (vga->r[0]<<6)|vga->n[0];
			if(vga->r[0] & 0x04)
				vga->sequencer[0x29] |= 0x01;
			else
				vga->sequencer[0x29] &= ~0x01;
			break;

		case 0x8C2E:			/* SuperSavage/IXC16 (let's try this -rsc) */
		case 0x8C10:			/* Savage MX/MV */
		case 0x8C12:			/* Savage4/IX-MV */
		case 0x8A22:			/* Savage4 */
		case 0x8A25:			/* ProSavage PN133 */
		case 0x8A26:			/* ProSavage KN133 */
		case 0x8D04:			/* ProSavage DDR, K.Okamoto */
			vga->sequencer[0x12] = (vga->r[0]<<6)|(vga->n[0] & 0x3F);
			vga->sequencer[0x39] &= ~0x01;
			vga->sequencer[0x29] &= ~0x1C;
			if(vga->r[0] & 0x04)
				vga->sequencer[0x29] |= (1<<2);
			if(vga->m[0] & 0x100)
				vga->sequencer[0x29] |= (1<<3);
			if(vga->n[0] & 0x40)
				vga->sequencer[0x29] |= (1<<4);
			break;

		default:
			vga->sequencer[0x12] = (vga->r[0]<<5)|vga->n[0];
			break;
		}
		vga->sequencer[0x13] = vga->m[0];
		vga->misc |= 0x0C;
	}

	/*
	 * Internal clock generator.
	 */
	vga->sequencer[0x15] &= ~0x31;
	vga->sequencer[0x15] |= 0x02;
	vga->sequencer[0x18] &= ~0x80;

	/*
	 * Start display FIFO fetch.
	 */
	x = (vga->crt[0]+vga->crt[4]+1)/2;
	vga->crt[0x3B] = x;
	if(x & 0x100)
		vga->crt[0x5D] |= 0x40;

	/*
	 * Display memory access control.
	 * Calculation of the M-parameter (Crt54) is
	 * memory-system and dot-clock dependent, the
	 * values below are guesses from dumping
	 * registers.
	 * The Savage4 does not document 0x54,
	 * but we leave this anyway.
	 */
	if(vga->mode->x <= 800)
		vga->crt[0x54] = 0xE8;
	else if(vga->mode->x <= 1024 && id != 0x8C12 && id != 0x8C2E)
		vga->crt[0x54] = 0xA8;
	else
		vga->crt[0x54] = 0x00/*0x48*/;

	ctlr->flag |= Finit;
}

static void
load(Vga* vga, Ctlr* ctlr)
{
	int id;
	ushort advfunc;

	s3generic.load(vga, ctlr);

	/*
	 * Load the PLL registers if necessary.
	 * Not sure if the variable-delay method of setting the
	 * PLL will work without a write here to vga->misc,
	 * so use the immediate-load method by toggling bit 5
	 * of Seq15 if necessary.
	 */
	vgaxo(Seqx, 0x12, vga->sequencer[0x12]);
	vgaxo(Seqx, 0x13, vga->sequencer[0x13]);
	id = (vga->crt[0x2D]<<8)|vga->crt[0x2E];
	switch(id){
	case 0x883D:				/* ViRGE/VX*/
		vgaxo(Crtx, 0x36, vga->crt[0x36]);
		break;
	case 0x8A10:				/* ViRGE/GX2 */
		vgaxo(Seqx, 0x29, vga->sequencer[0x29]);
		break;
	case 0x8C2E:				/* SuperSavage/IXC16 (let's try this -rsc) */
	case 0x8C12:				/* Savage4/IX-MV */
		vgaxo(Crtx, 0x90, vga->crt[0x90]);
		vgaxo(Crtx, 0x91, vga->crt[0x91]);
		/*FALLTHROUGH*/
	case 0x8A22:				/* Savage4 */
	case 0x8A25:				/* ProSavage PN133 */
	case 0x8A26:				/* ProSavage KN133 */
	case 0x8D04:				/* ProSavage DDR, K.Okamoto */
		vgaxo(Seqx, 0x29, vga->sequencer[0x29]);
		vgaxo(Seqx, 0x39, vga->sequencer[0x39]);
		break;
	}
	if((vga->misc & 0x0C) == 0x0C)
		vgaxo(Seqx, 0x15, vga->sequencer[0x15]|0x20);
	vgaxo(Seqx, 0x15, vga->sequencer[0x15]);
	vgaxo(Seqx, 0x18, vga->sequencer[0x18]);

	vgaxo(Crtx, 0x60, vga->crt[0x60]);
	vgaxo(Crtx, 0x63, vga->crt[0x63]);
	vgaxo(Crtx, 0x65, vga->crt[0x65]);
	vgaxo(Crtx, 0x66, vga->crt[0x66]);
	vgaxo(Crtx, 0x67, vga->crt[0x67]);

	switch(id){

	case 0x8810:				/* Microsoft Virtual PC 2004 */
	case 0x8811:				/* Trio64+ */
		advfunc = 0x0000;
		if(ctlr->flag & Uenhanced)
			advfunc = 0x0001;
		outportw(0x4AE8, advfunc);
		break;
	case 0x8901:				/* Trio64V2 */
	case 0x8A01:				/* ViRGE/[DG]X */
		vgaxo(Crtx, 0x90, vga->crt[0x90]);
		vgaxo(Crtx, 0x91, vga->crt[0x91]);
		break;
	case 0x8A10:				/* ViRGE/GX2 */
		vgaxo(Crtx, 0x90, vga->crt[0x90]);
		vgaxo(Crtx, 0x31, vga->crt[0x31]);
		vgaxo(Crtx, 0x13, vga->crt[0x13]);
		vgaxo(Crtx, 0x51, vga->crt[0x51]);
		vgaxo(Crtx, 0x85, vga->crt[0x85]);
		break;
	case 0x8D04:				/* ProSavage DDR, K.Okamoto */
		vgaxo(Crtx, 0x90, vga->crt[0x90]);		//K.Okamoto
		vgaxo(Crtx, 0x91, vga->crt[0x91]);		//K.Okamoto
	case 0x8C2E:				/* SuperSavage/IXC16 (let's try this -rsc) */
	case 0x8C12:				/* Savage4/IX-MV */
	case 0x8A22:				/* Savage4 */
	case 0x8A25:				/* ProSavage PN133 */
	case 0x8A26:				/* ProSavage KN133 */
		vgaxo(Crtx, 0x31, vga->crt[0x31]);
		vgaxo(Crtx, 0x13, vga->crt[0x13]);
		vgaxo(Crtx, 0x51, vga->crt[0x51]);
		vgaxo(Crtx, 0x85, vga->crt[0x85]);
		vgaxo(Crtx, 0x50, vga->crt[0x50]);
		break;
	}
}

static void
dump(Vga* vga, Ctlr* ctlr)
{
	int i, id;
	ulong dclk, m, n, r;

	s3generic.dump(vga, ctlr);
	printitem(ctlr->name, "Crt70");
	for(i = 0x70; i < 0x99; i++)
		printreg(vga->crt[i]);

	printitem(ctlr->name, "Seq08");
	for(i = 0x08; i < 0x10; i++)
		printreg(vga->sequencer[i]);
	printitem(ctlr->name, "Seq10");
	for(i = 0x10; i < 0x50; i++)
		printreg(vga->sequencer[i]);
	id = (vga->crt[0x2D]<<8)|vga->crt[0x2E];
	switch(id){
	default:
		break;

	case 0x8812:				/* Aurora64V+ */
	case 0x8C2E:				/* SuperSavage/IXC16 (let's try this -rsc) */
	case 0x8C12:				/* Savage4/IX-MV */
		printitem(ctlr->name, "Seq50");
		for(i = 0x50; i < 0x70; i++)
			printreg(vga->sequencer[i]);
		break;
	}

	printitem(ctlr->name, "Crt2D");
	printreg(vga->crt[0x2D]);
	printreg(vga->crt[0x2E]);
	printreg(vga->crt[0x2F]);

	m = vga->sequencer[0x13] & vga->m[1];
	n = vga->sequencer[0x12] & vga->n[1];
	r = (vga->sequencer[0x12]>>5) & 0x03;

	switch(id){
	case 0x8812:				/* Aurora64V+ */
		r = (vga->sequencer[0x12]>>6) & 0x03;
		break;
	case 0x8A01:				/* ViRGE/[DG]X */
		r = (vga->sequencer[0x12]>>5) & 0x07;
		break;
	case 0x8A10:				/* ViRGE/GX2 */
		r = (vga->sequencer[0x12]>>6) & 0x03;
		r |= (vga->sequencer[0x29] & 0x01)<<2;
		break;
	case 0x8C2E:				/* SuperSavage/IXC16 (let's try this -rsc) */
	case 0x8C12:				/* Savage4/IX-MV */
	case 0x8A22:				/* Savage4 */
	case 0x8A25:				/* ProSavage PN133 */
	case 0x8A26:				/* ProSavage KN133 */
	case 0x8D04:				/* Prosavage DDR, K.Okamoto */
		m = vga->sequencer[0x13] & 0xFF;
		if(vga->sequencer[0x29] & (1<<3))
			m |= 0x100;
		if(vga->sequencer[0x29] & (1<<4))
			n |= 0x40;
		r = (vga->sequencer[0x12]>>6) & 0x03;
		r |= (vga->sequencer[0x29] & (1<<2));
		break;
	}

	dclk = (m+2)*RefFreq;
	dclk /= (n+2)*(1<<r);
	printitem(ctlr->name, "dclk m n r");
	Bprint(&stdout, "%9ld %8ld       - %8ld %8ld\n", dclk, m, n, r);

	m = vga->sequencer[0x11] & 0x7F;
	n = vga->sequencer[0x10] & 0x1F;
	r = (vga->sequencer[0x10]>>5) & 0x03;	/* might be GX/2 specific */
	dclk = (m+2)*RefFreq;
	dclk /= (n+2)*(1<<r);
	printitem(ctlr->name, "mclk m n r");
	Bprint(&stdout, "%9ld %8ld       - %8ld %8ld\n", dclk, m, n, r);
}

Ctlr virge = {
	"virge",			/* name */
	snarf,				/* snarf */
	options,			/* options */
	init,				/* init */
	load,				/* load */
	dump,				/* dump */
};