📄 fuzzypid.mdl
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SourceBlock "fuzblock/Fuzzy Logic \nController"
SourceType "FIS"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
fis " fuzzy_pid_rules"
}
Block {
BlockType Gain
Name "Gain"
Position [300, 145, 330, 175]
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Mux
Name "Mux"
Ports [2, 1]
Position [345, 92, 350, 183]
ShowName off
Inputs "2"
DisplayOption "bar"
}
Block {
BlockType Scope
Name "Scope"
Ports [1]
Position [420, 264, 450, 296]
Floating off
Location [161, 218, 815, 525]
Open off
NumInputPorts "1"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
}
TimeRange "200"
YMin "0"
YMax "1.5"
DataFormat "StructureWithTime"
SampleTime "0.1"
}
Block {
BlockType Step
Name "Step"
Position [95, 135, 125, 165]
Time "0"
SampleTime "0"
}
Block {
BlockType SubSystem
Name "Subsystem"
Ports [4, 1]
Position [260, 198, 315, 242]
Orientation "left"
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
FunctionWithSeparateData off
MaskHideContents off
System {
Name "Subsystem"
Location [19, 105, 573, 696]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "156"
Block {
BlockType Inport
Name "e"
Position [25, 168, 55, 182]
IconDisplay "Port number"
}
Block {
BlockType Inport
Name "kp"
Position [125, 78, 155, 92]
Port "2"
IconDisplay "Port number"
}
Block {
BlockType Inport
Name "ki"
Position [125, 148, 155, 162]
Port "3"
IconDisplay "Port number"
}
Block {
BlockType Inport
Name "kd"
Position [125, 218, 155, 232]
Port "4"
IconDisplay "Port number"
}
Block {
BlockType Sum
Name "Add"
Ports [3, 1]
Position [230, 125, 260, 205]
Inputs "+++"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
OutScaling "2^-10"
SaturateOnIntegerOverflow off
}
Block {
BlockType Derivative
Name "Derivative1"
Position [85, 230, 115, 260]
}
Block {
BlockType Gain
Name "Gain"
Position [85, 90, 115, 120]
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Integrator
Name "Integrator"
Ports [1, 1]
Position [85, 160, 115, 190]
IgnoreLimit off
}
Block {
BlockType Product
Name "Product"
Ports [2, 1]
Position [170, 76, 205, 114]
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Product
Name "Product1"
Ports [2, 1]
Position [170, 146, 205, 184]
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Product
Name "Product2"
Ports [2, 1]
Position [170, 216, 205, 254]
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Outport
Name "Out1"
Position [275, 158, 305, 172]
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "kp"
SrcPort 1
DstBlock "Product"
DstPort 1
}
Line {
SrcBlock "Gain"
SrcPort 1
DstBlock "Product"
DstPort 2
}
Line {
SrcBlock "ki"
SrcPort 1
DstBlock "Product1"
DstPort 1
}
Line {
SrcBlock "kd"
SrcPort 1
DstBlock "Product2"
DstPort 1
}
Line {
SrcBlock "Integrator"
SrcPort 1
DstBlock "Product1"
DstPort 2
}
Line {
SrcBlock "Derivative1"
SrcPort 1
DstBlock "Product2"
DstPort 2
}
Line {
SrcBlock "e"
SrcPort 1
Points [5, 0]
Branch {
DstBlock "Integrator"
DstPort 1
}
Branch {
Points [0, -70]
DstBlock "Gain"
DstPort 1
}
Branch {
Points [0, 70]
DstBlock "Derivative1"
DstPort 1
}
}
Line {
SrcBlock "Product"
SrcPort 1
Points [5, 0]
DstBlock "Add"
DstPort 1
}
Line {
SrcBlock "Product1"
SrcPort 1
DstBlock "Add"
DstPort 2
}
Line {
SrcBlock "Product2"
SrcPort 1
Points [5, 0]
DstBlock "Add"
DstPort 3
}
Line {
SrcBlock "Add"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
}
}
Block {
BlockType Sum
Name "Subtract"
Ports [2, 1]
Position [150, 142, 180, 173]
Inputs "+-"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
OutScaling "2^-10"
SaturateOnIntegerOverflow off
}
Block {
BlockType TransferFcn
Name "Transfer Fcn"
Position [255, 262, 375, 298]
Numerator "[523500]"
Denominator "[1 87.35 10470 0]"
}
Block {
BlockType SignalViewerScope
Name "Scope1"
Ports []
Position [35, 50, 75, 90]
IOType "viewer"
Location [188, 365, 512, 604]
Open off
NumInputPorts "1"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
}
ShowDataMarkers off
ShowLegends off
DataFormat "Array"
MaxDataPoints "7500"
RefreshTime 0.035000
Disabled off
}
Line {
SrcBlock "Step"
SrcPort 1
DstBlock "Subtract"
DstPort 1
}
Line {
SrcBlock "Mux"
SrcPort 1
DstBlock "Fuzzy Logic \nController"
DstPort 1
}
Line {
SrcBlock "Abs1"
SrcPort 1
DstBlock "Mux"
DstPort 1
}
Line {
SrcBlock "Subtract"
SrcPort 1
Points [5, 0]
Branch {
DstBlock "Abs1"
DstPort 1
}
Branch {
Points [0, 0]
Branch {
DstBlock "Derivative"
DstPort 1
}
Branch {
Points [0, 30; 140, 0]
DstBlock "Subsystem"
DstPort 1
}
}
}
Line {
SrcBlock "Derivative"
SrcPort 1
DstBlock "Abs2"
DstPort 1
}
Line {
SrcBlock "Abs2"
SrcPort 1
DstBlock "Gain"
DstPort 1
}
Line {
SrcBlock "Gain"
SrcPort 1
DstBlock "Mux"
DstPort 2
}
Line {
SrcBlock "Transfer Fcn"
SrcPort 1
Points [10, 0]
Branch {
DstBlock "Scope"
DstPort 1
}
Branch {
Points [0, 35; -255, 0]
DstBlock "Subtract"
DstPort 2
}
}
Line {
SrcBlock "Subsystem"
SrcPort 1
Points [-15, 0]
DstBlock "Transfer Fcn"
DstPort 1
}
Line {
SrcBlock "Demux"
SrcPort 1
DstBlock "Subsystem"
DstPort 2
}
Line {
SrcBlock "Demux"
SrcPort 2
DstBlock "Subsystem"
DstPort 3
}
Line {
SrcBlock "Demux"
SrcPort 3
DstBlock "Subsystem"
DstPort 4
}
Line {
SrcBlock "Fuzzy Logic \nController"
SrcPort 1
Points [5, 0; 0, 85]
DstBlock "Demux"
DstPort 1
}
}
}
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