m5282.h

zigbee 飞思卡尔 音频传输 基于ucos的所有源码

/******************************************************************
 *
 * Filename:   m5282.h                                         
 *                                                              
 * This is a general include file for software
 * development on the MCF5282 ColdFire platform.
 * It does not include all the registers, just enough
 * to do some simple testing.
 *
 *
 * Author  : Carlton Heyer
 *           Avnet, Inc. - Avnet Design Services (ADS)
 *           [e-mail]
 * Created : 3/24/2004
 *
 ********************************************************************/

//#define	MBAR	0x10000000	

/* SIM28 System Configuration Registers */
//#define	M5272_SCR    (MBAR+0x000)

/* I/O Port Registers */
/* Port A Registers   */
//#define	M5272_PACNT  (MBAR+0x0080)
//#define	M5272_PADDR  (MBAR+0x0084)	
//#define	M5272_PADAT  (MBAR+0x0086)
/* Port B Registers   */	
//#define	M5272_PBCNT  (MBAR+0x0088)
//#define	M5272_PBDDR  (MBAR+0x008C)
//#define	M5272_PBDAT  (MBAR+0x008E)
/* Port C Registers   */
//#define	M5272_PCDDR  (MBAR+0x0094)
//#define	M5272_PCDAT  (MBAR+0x0096)
/* Port D Registers   */
//#define	M5272_PDCNT  (MBAR+0x0098)


/* QSPI Registers */
//#define	M5272_QMR    (MBAR+0x00A0)
//#define	M5272_QDLYR  (MBAR+0x00A4)
//#define	M5272_QWR    (MBAR+0x00A8)
//#define	M5272_QIR    (MBAR+0x00AC)
//#define	M5272_QAR    (MBAR+0x00B0)
//#define	M5272_QDR    (MBAR+0x00B4)

/* Timer Registers   */
    /* Timer 0 Registers */
//#define  M5272_TMR0	  (MBAR+0x0200)   /* Mode Reg       */
//#define  M5272_TRR0    (MBAR+0x0204)   /* Reference Reg  */
//#define  M5272_TCR0    (MBAR+0x0200)   /* Capture Reg    */
//#define  M5272_TCN0    (MBAR+0x020C)   /* Counter        */
//#define  M5272_TER0    (MBAR+0x0210)   /* Event Reg      */

    /* Timer 1 Registers */
//#define  M5272_TMR1     (MBAR+0x0220)  /* Mode Reg       */
//#define  M5272_TRR1     (MBAR+0x0224)  /* Reference Reg	*/
//#define  M5272_TCR1     (MBAR+0x0220)  /* Capture Reg    */
//#define  M5272_TCN1     (MBAR+0x022C)  /* Counter        */
//#define  M5272_TER1     (MBAR+0x0230)  /* Event Reg      */

    /* Timer 2 Registers */
//#define  M5272_TMR2     (MBAR+0x0240)  /* Mode Reg       */
//#define  M5272_TRR2     (MBAR+0x0244)  /* Reference Reg  */
//#define  M5272_TCR2     (MBAR+0x0240)  /* Capture Reg    */
//#define  M5272_TCN2     (MBAR+0x024C)  /* Counter        */
//#define  M5272_TER2     (MBAR+0x0250)  /* Event Reg      */

    /* Timer 3 Registers */
//#define  M5272_TMR3     (MBAR+0x0260)  /* Mode Reg       */
//#define  M5272_TRR3     (MBAR+0x0264)  /* Reference Reg  */
//#define  M5272_TCR3     (MBAR+0x0260)  /* Capture Reg    */
//#define  M5272_TCN3     (MBAR+0x026C)  /* Counter        */
//#define  M5272_TER3     (MBAR+0x0270)  /* Event Reg      */

/* Interrupt Control Registers */
//#define  M5272_ICR1     (MBAR+0x0020)   /* interrupt control register 1 */
//#define  M5272_ICR2     (MBAR+0x0024)   /* interrupt control register 2 */
//#define  M5272_ICR3     (MBAR+0x0028)   /* interrupt control register 3 */
//#define  M5272_ICR4     (MBAR+0x002C)   /* interrupt control register 4 */
//#define  M5272_ISR      (MBAR+0x0030)   /* interrupt source register    */
//#define  M5272_PITR     (MBAR+0x0034)   /* programmable interrupt transition register */
//#define  M5272_PIWR     (MBAR+0x0038)   /* programmable interrupt wakeup register     */
//#define  M5272_PIVR     (MBAR+0x003F)   /* programmable interrupt vector register     */

/******************************************************
*******************************************************
			MCF5282 Register Definitions
*******************************************************
******************************************************/
#define REF_A(x)	(*((volatile uint8 *)(x)))
#define REF_B(x)	(*((volatile uint16 *)(x)))
#define REF_C(x)	(*((volatile uint32 *)(x)))

#define IPSBAR		0x40000000

//	General Purpost Timer A Registers
#define GPTASYSCR1	REF_A(IPSBAR + 0x1a0006)	// GPTA Control reg 1
#define GPTADR		REF_A(IPSBAR + 0x1a001d)	// GPTA Data Reg
#define GPTADDR		REF_A(IPSBAR + 0x1a001e)	// GPTA Data Direction

//	General Purpose Timer B Registers
#define GPTBSYSCR1	REF_A(IPSBAR + 0x1b0006)
#define GPTBDR		REF_A(IPSBAR + 0x1b001d)
#define GPTBDDR		REF_A(IPSBAR + 0x1b001e)


//	GPIO Registers
#define PORT_TC		REF_A(IPSBAR + 0x10000f)
#define PORT_TD		REF_A(IPSBAR + 0x100010)
#define DDR_TC		REF_A(IPSBAR + 0x100023)
#define DDR_TD		REF_A(IPSBAR + 0x100024)
#define DR_TC		REF_A(IPSBAR + 0x100037)
#define DR_TD		REF_A(IPSBAR + 0x100038)

//	Interrupt Controller 0
#define IPRH0		REF_C(IPSBAR + 0xc00)
#define IPRL0		REF_C(IPSBAR + 0xc04)
#define IMRH0		REF_C(IPSBAR + 0xc08)
#define IMRL0		REF_C(IPSBAR + 0xc0c)
#define INTFRCH0	REF_C(IPSBAR + 0xc10)
#define INTFRCL0	REF_C(IPSBAR + 0xc14)
#define ILRR0		REF_A(IPSBAR + 0xc18)
#define IACKLPR0	REF_A(IPSBAR + 0xc19)
#define ICR001		REF_A(IPSBAR + 0xc41)
#define ICR002		REF_A(IPSBAR + 0xc42)
#define ICR003		REF_A(IPSBAR + 0xc43)
#define ICR004		REF_A(IPSBAR + 0xc44)
#define ICR055		REF_A(IPSBAR + 0xc77)

//	Programmable Interrupt Timer (PIT)
#define	PIT0		0x00150000
#define	PIT1		0x00160000
#define	PIT2		0x00170000
#define	PIT3		0x00180000
#define	PCSR		0x0
#define	PMR			0x2
#define	PIT0_PCSR	REF_B(IPSBAR + PIT0 + PCSR)
#define	PIT0_PMR	REF_B(IPSBAR + PIT0 + PMR)
#define	DOZE		0x00000040
#define	HALTED		0x00000020
#define	OVW			0x00000010
#define	PIE			0x00000008
#define	PIF			0x00000004
#define	RLD			0x00000002
#define	EN			0x00000001



#define FLASHBASE	0xFF800000