📄 power_main.c
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if (argc == 3)
{
switch (test)
{
case 0: /* 244 Hz */
clock_pll(0, 0, PLL_DISABLE);
clock_lpd(32768);
break;
case 1: /* 16 MHz */
clock_pll(REF_CLK_KHZ, 16000, 0);
break;
case 2: /* 32 MHz */
clock_pll(REF_CLK_KHZ, 32000, 0);
break;
case 3: /* 48 MHz */
clock_pll(REF_CLK_KHZ, 48000, 0);
break;
case 4: /* 64 MHz */
clock_pll(REF_CLK_KHZ, 64000, 0);
break;
case 5: /* 80 MHz */
clock_pll(REF_CLK_KHZ, 80000, 0);
break;
default:
printf(INVALUE,argv[2]);
return;
}
}
if (i != 99)
{
MCF_SCM_PPMRS = MCF_SCM_PPMRS_DISABLE_ALL;
MCF_SCM_PPMRC = MCF_SCM_PPMRC_CLEAR_CDG;
MCF_SCM_PPMRC = i;
}
abort_flag = FALSE;
while (abort_flag == FALSE)
{
nop();
}
}
/*
* If no argument was passed in, then cycle through all the valid
* ones. The INTC is always enabled so that the ABORT button can
* be used to cycle through the valid gated clocks. A baseline
* should be taken with just the core and with the core plus the
* INTC so that the INTC power can be subtracted from the power
* measured here.
*/
else
{
int test;
int8 clocks[] = { 0, 4, 5, 6, 7, 9, 10, 13, 14, 15, 16,
32, 35, 36, 39, 40, 41, 42, 43, 99};
for (test = 0; test < 6; test++)
{
printf("-- Test %d --\n", test);
for (i = 0; i < sizeof(clocks); i++)
{
printf("Gated Clock #%d\n", clocks[i]);
/* Wait for the UART to finish transmitting */
while(!(MCF_UART_UCSR(TERMINAL_PORT) & MCF_UART_USR_TXEMP)) {};
switch (test)
{
case 0: /* 244 Hz */
clock_pll(0, 0, PLL_DISABLE);
clock_lpd(32768);
break;
case 1: /* 16 MHz */
clock_pll(REF_CLK_KHZ, 16000, 0);
break;
case 2: /* 32 MHz */
clock_pll(REF_CLK_KHZ, 32000, 0);
break;
case 3: /* 48 MHz */
clock_pll(REF_CLK_KHZ, 48000, 0);
break;
case 4: /* 64 MHz */
clock_pll(REF_CLK_KHZ, 64000, 0);
break;
case 5: /* 80 MHz */
clock_pll(REF_CLK_KHZ, 80000, 0);
break;
}
if (clocks[i] != 99)
{
min_pwr_config();
MCF_SCM_PPMRC = clocks[i];
}
abort_flag = FALSE;
while (abort_flag == FALSE)
{
nop();
}
clock_lpd(1);
clock_pll(REF_CLK_KHZ, sys_clk_khz, 0);
max_pwr_config();
}
}
}
}
/********************************************************************/
void
setshow_sysclk (int argc, char **argv)
{
int success, sysclk;
/* Set */
if (argv[2] != NULL)
{
/* Wait for the UART to finish transmitting */
while(!(MCF_UART_UCSR(TERMINAL_PORT) & MCF_UART_USR_TXEMP)) {};
/* Get user input (in KHz) */
sysclk = get_value(argv[2],&success,10);
if (success == 0)
{
printf(INVALUE,argv[2]);
return;
}
if (sysclk == 0)
{
/* Disable the PLL */
sys_clk_khz = (clock_pll(REF_CLK_KHZ, sysclk, PLL_DISABLE) /
clock_lpd(0));
}
else
{
/* Set the PLL to the desired system clock */
sys_clk_khz = (clock_pll(REF_CLK_KHZ, sysclk, 0) /
clock_lpd(0));
}
/* Re-init the UART with the new system clock setting */
uart_init(TERMINAL_PORT, sys_clk_khz, baud, 0);
printf("System Clock: %d KHz\n", sys_clk_khz);
}
/* Show */
else
printf("%d KHz", sys_clk_khz);
}
/********************************************************************/
void
setshow_clkout (int argc, char **argv)
{
/* Set */
if (argv[2] != NULL)
{
if (strcasecmp(argv[2], "on") == 0)
{
clkout = ON;
clock_clkout_enable();
cpu_pstddata_enable();
}
else if (strcasecmp(argv[2], "off") == 0)
{
clkout = OFF;
clock_clkout_disable();
cpu_pstddata_disable();
}
else
printf(INVALUE,argv[2]);
}
/* Show */
else
{
if (clkout == ON)
printf("ON");
else
printf("OFF");
}
}
/********************************************************************/
void
setshow_lpd (int argc, char **argv)
{
int success, lpd;
/* Set */
if (argv[2] != NULL)
{
/* Wait for the UART to finish transmitting */
while(!(MCF_UART_UCSR(TERMINAL_PORT) & MCF_UART_USR_TXEMP)) {};
lpd = (uint8) get_value(argv[2],&success,10);
if (success == 0)
{
printf(INVALUE,argv[2]);
return;
}
sys_clk_khz = clock_pll(REF_CLK_KHZ, 0, 0) / clock_lpd(lpd);
/* Re-init the UART with the new system clock setting */
uart_init(TERMINAL_PORT, sys_clk_khz, baud, 0);
}
/* Show */
else
printf("%d", clock_lpd(0));
}
/********************************************************************/
void
setshow_stpmd (int argc, char **argv)
{
int success, temp;
/* Set */
if (argv[2] != NULL)
{
temp = (uint8) get_value(argv[2],&success,10);
if (success == 0)
{
printf(INVALUE,argv[2]);
return;
}
if ((temp > 3) || (temp < 0))
{
printf(INVALUE,argv[2]);
return;
}
stpmd = temp;
}
/* Show */
else
printf("b'%02b",stpmd);
}
/********************************************************************/
void
setshow_lvdse (int argc, char **argv)
{
int success, temp;
/* Set */
if (argv[2] != NULL)
{
temp = (uint8) get_value(argv[2],&success,10);
if (success == 0)
{
printf(INVALUE,argv[2]);
return;
}
if ((temp > 1) || (temp < 0))
{
printf(INVALUE,argv[2]);
return;
}
lvdse = temp;
}
/* Show */
else
printf("b'%b",lvdse);
}
/********************************************************************/
void
setshow_xipl (int argc, char **argv)
{
int success, temp;
/* Set */
if (argv[2] != NULL)
{
temp = (uint8) get_value(argv[2],&success,10);
if (success == 0)
{
printf(INVALUE,argv[2]);
return;
}
if ((temp > 7) || (temp < 0))
{
printf(INVALUE,argv[2]);
return;
}
xipl = temp;
}
/* Show */
else
printf("b'%03b",xipl);
}
/********************************************************************/
void
setshow_baud (int argc, char **argv)
{
int success, temp;
/* Set */
if (argv[2] != NULL)
{
temp = get_value(argv[2],&success,10);
if (success == 0)
{
printf(INVALUE,argv[2]);
return;
}
switch (temp)
{
case 110:
case 300:
case 600:
case 1200:
case 2400:
case 4800:
case 9600:
case 14400:
case 19200:
case 38400:
case 57600:
case 115200:
baud = temp;
break;
default:
printf(INVALUE,argv[2]);
return;
}
/* Re-init the UART with the new system clock setting */
uart_init(TERMINAL_PORT, sys_clk_khz, baud, 0);
}
/* Show */
else
printf("%d", baud);
}
/********************************************************************/
void
setshow_step (int argc, char **argv)
{
int success, temp;
/* Set */
if (argv[2] != NULL)
{
temp = get_value(argv[2],&success,10);
if (success == 0)
{
printf(INVALUE,argv[2]);
return;
}
clk_step = temp;
}
/* Show */
else
printf("%d", clk_step);
}
/********************************************************************/
void
setshow_pwrcfg (int argc, char **argv)
{
/* Set */
if (argv[2] != NULL)
{
if (strcasecmp(argv[2], "min") == 0)
{
tpwrcfg = PWR_MIN;
}
else if (strcasecmp(argv[2], "max") == 0)
{
tpwrcfg = PWR_MAX;
}
else if (strcasecmp(argv[2], "typ") == 0)
{
tpwrcfg = PWR_TYP;
}
else
{
printf(INVALUE,argv[2]);
return;
}
}
/* Show */
else
{
switch (tpwrcfg)
{
case PWR_MIN:
printf("MIN");
break;
case PWR_TYP:
printf("TYP");
break;
case PWR_MAX:
default:
printf("MAX");
}
}
}
/********************************************************************/
void
min_pwr_config(void)
{
/*
* Put clock gating into the "minimum functional" configuration
*/
MCF_SCM_PPMRH = 0
| MCF_SCM_PPMRH_CDPORTS
/* | MCF_SCM_PPMRH_CDEPORT */
| MCF_SCM_PPMRH_CDPIT0
| MCF_SCM_PPMRH_CDPIT1
| MCF_SCM_PPMRH_CDADC
| MCF_SCM_PPMRH_CDGPT
| MCF_SCM_PPMRH_CDPWM
| MCF_SCM_PPMRH_CDFCAN
/* | MCF_SCM_PPMRH_CDCFM */;
MCF_SCM_PPMRL = 0
/* | MCF_SCM_PPMRL_CDG */
| MCF_SCM_PPMRL_CDEIM
| MCF_SCM_PPMRL_CDDMA
| MCF_SCM_PPMRL_CDUART0
| MCF_SCM_PPMRL_CDUART1
| MCF_SCM_PPMRL_CDUART2
| MCF_SCM_PPMRL_CDI2C
| MCF_SCM_PPMRL_CDQSPI
| MCF_SCM_PPMRL_CDDTIM0
| MCF_SCM_PPMRL_CDDTIM1
| MCF_SCM_PPMRL_CDDTIM2
| MCF_SCM_PPMRL_CDDTIM3
/* | MCF_SCM_PPMRL_CDINTC0 */;
/* Disable the CLKOUT and PST/DDATA signals */
clock_clkout_disable();
cpu_pstddata_disable();
if (running_in_sram)
{
/* Disable FLASHBAR */
mcf5xxx_wr_rambar0(0);
/* Disable CFM clock */
MCF_SCM_PPMRS = MCF_SCM_PPMRS_DISABLE_CFM;
}
else
{
/* Disable SRAM instruction accesses */
mcf5xxx_wr_rambar1(SRAM_ADDRESS + 0x35);
}
cpwrcfg = PWR_MIN;
}
/********************************************************************/
void
typ_pwr_config(void)
{
/*
* Put clock gating into a "typical" configuration
*/
MCF_SCM_PPMRH = 0
| MCF_SCM_PPMRH_CDPORTS
/* | MCF_SCM_PPMRH_CDEPORT */
| MCF_SCM_PPMRH_CDPIT0
| MCF_SCM_PPMRH_CDPIT1
| MCF_SCM_PPMRH_CDADC
| MCF_SCM_PPMRH_CDGPT
| MCF_SCM_PPMRH_CDPWM
| MCF_SCM_PPMRH_CDFCAN
/* | MCF_SCM_PPMRH_CDCFM */;
MCF_SCM_PPMRL = 0
/* | MCF_SCM_PPMRL_CDG */
| MCF_SCM_PPMRL_CDEIM
| MCF_SCM_PPMRL_CDDMA
/* | MCF_SCM_PPMRL_CDUART0 */
| MCF_SCM_PPMRL_CDUART1
| MCF_SCM_PPMRL_CDUART2
| MCF_SCM_PPMRL_CDI2C
| MCF_SCM_PPMRL_CDQSPI
| MCF_SCM_PPMRL_CDDTIM0
| MCF_SCM_PPMRL_CDDTIM1
| MCF_SCM_PPMRL_CDDTIM2
| MCF_SCM_PPMRL_CDDTIM3
/* | MCF_SCM_PPMRL_CDINTC0 */;
/* Disable the CLKOUT and PST/DDATA signals */
clock_clkout_disable();
cpu_pstddata_disable();
if (running_in_sram)
{
/* Disable FLASHBAR */
mcf5xxx_wr_rambar0(0);
/* Disable CFM clock */
MCF_SCM_PPMRS = MCF_SCM_PPMRS_DISABLE_CFM;
}
else
{
/* Disable SRAM instruction accesses */
mcf5xxx_wr_rambar1(SRAM_ADDRESS + 0x35);
}
cpwrcfg = PWR_TYP;
}
/********************************************************************/
void
max_pwr_config(void)
{
/* Restore to default configuration with all clocks, etc. on */
MCF_SCM_PPMRC = MCF_SCM_PPMRC_ENABLE_ALL;
clock_clkout_enable();
cpu_pstddata_enable();
mcf5xxx_wr_rambar0(FLASH_ADDRESS + 0x21);
mcf5xxx_wr_rambar1(SRAM_ADDRESS + 0x21);
cpwrcfg = PWR_MAX;
}
/********************************************************************/
void
set_pwr_config(int cfg)
{
switch (cfg)
{
case PWR_MIN:
min_pwr_config();
break;
case PWR_TYP:
typ_pwr_config();
break;
case PWR_MAX:
default:
max_pwr_config();
}
}
/********************************************************************/
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