lcdc.h

ch7013驱动

#ifndef _LCDC_H
#define _LCDC_H

#define LCDWIDTH	640
#define LCDHIGHT	480

#define _16Bit_565

#define VS_BASE     0x30100000

//Macro for SIZE register setting
#define XMAX	((LCDWIDTH/16)	<< 20)
#define YMAX	(LCDHIGHT)

//Macro for PCR register setting
#define TFT		(1 << 31)   // Mode of TFT      1-Active   0-Passive
#define COLOR	(1 << 30)   // 1-Color    0- Gray
#define PBSIZE	(0 << 28)   //Width of LCD DataBus
                            //          0'b00 - 1bit
                            //          0'b01 - 2bit
                            //          0'b10 - 3bit
                            //          0'b11 - 4bit
#define BPIX	(4 << 25)   //Bits Per Pixel
                            //          0'b000  1bpp
                            //          0'b001  2bpp
                            //          0'b010  4bpp
                            //          0'b011  (Reserve)
                            //          0'b100  16bpp
                            //          0'b11x  (Reserve)
                            //          0'b1x1  (Reserve)
#define PIXPOL	(0 << 24)   //Polarity of Pixel     1 - Low    0 - High
#define FLMPOL	(1 << 23)   //Polarity of Frame Synchronization     1 - Low    0 - High
#define LPPOL	(1 << 22)   //Polarity of Line Synchronization  1 - Low    0 - High
#define CLKPOL	(0 << 21)   //Polarity of Shifter Clock
                            //              for TFT MODE            for STN MODE
                            //          1 - Fall Edge               1 - Rise Edge
                            //          0 - Rise Edge               0 - Fall Edge
#define OEPOL	(0 << 20)   //Polarity of OE        1 - Low    0 - High
#define END_SEL	(0 << 18)   //Indian Order Select    1 - Big Indian    0 - Litter Indian
#define ACD_SEL	(0 << 15)   //Clock Source of ACD       1 - LP/HSYN    0 - FLM
#define ACD		(0 << 8 )   //Cycles of ACD invert   ( not use for Active Mode(TFT=1) )
//#define PCD		(5)         //Cycles of Pixel Clock 
#define PCD		(1)         //Cycles of Pixel Clock 

//Macro for HCR regiter setting
#define H_WIDTH		(50 << 26)  // Width of Horizontal Synchronize Signal
#define H_WAIT_1	(15 << 8)   //Cycles between the last Data and the next Horizontal Syn.
#define H_WAIT_2	(102)       //Cycles between Horizontal Syn. disable edge and the first Data

//Macro for VCR register setting
#define V_WIDTH 	    (3 << 26) //Width of Vertical Synchronize Signal
#define PASS_FRAME_WAIT (0 <<16)    //
#define V_WAIT_1        (10 << 8)   //Cycles between OE disable edge and next fram's Vertical Syn enbale edge
#define V_WAIT_2        (30)        //Cycles between Vertical Syn disable edge and next frams's OE

//Macro for LGPR register setting
#define GRAY	    (4)

//Macro for PWMR register setting
#define SCR         (0 << 9)    // Clock source.
                                //          0'b00 - Line Pulse
                                //          0'b01 - Pixel colck
                                //          0'b10 - LCD colck
                                //          0'b11 - (Reserve)
#define CC_EN       (0 << 8)    //Contrast Enable   1 - Enable   0 - Disable
#define PW          (64)    // the amount of output pulses for Contrast

//Macro for DMACR register setting
#define BL          (1 << 31)   //Burst Length of DMA    1 - Fixed Length    0 - Flexible Length
#define HM          (7 << 16)   //High Flag of DMA request
#define TM          (3)     //Low Flag of DMA request



// Macro for COLOR
#ifdef _16Bit_565
#define     RED         0xF800
#define     GREEN       0x07E0
#define     BLUE        0x001F
#endif

#ifdef _15Bit_555
#define     RED         0x7C00
#define     GREEN       0x03E0
#define     BLUE        0x001F
#endif

#endif