📄 gfd_reg.h
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#define USB_CFGINTERFACE16 (BASE_USBDEVICE+0X06c) // ;cfg_interface register
#define USB_CFGINTERFACE17 (BASE_USBDEVICE+0X070) // ;cfg_interface register
#define USB_CFGINTERFACE18 (BASE_USBDEVICE+0X074) // ;cfg_interface register
#define USB_CFGINTERFACE19 (BASE_USBDEVICE+0X078) // ;cfg_interface register
#define USB_CFGINTERFACE20 (BASE_USBDEVICE+0X07c) // ;cfg_interface register
#define USB_CFGINTERFACE21 (BASE_USBDEVICE+0X080) // ;cfg_interface register
#define USB_CFGINTERFACE22 (BASE_USBDEVICE+0X084) // ;cfg_interface register
#define USB_CFGINTERFACE23 (BASE_USBDEVICE+0X088) // ;cfg_interface register
#define USB_CFGINTERFACE24 (BASE_USBDEVICE+0X08c) // ;cfg_interface register
#define USB_CFGINTERFACE25 (BASE_USBDEVICE+0X090) // ;cfg_interface register
#define USB_CFGINTERFACE26 (BASE_USBDEVICE+0X094) // ;cfg_interface register
#define USB_CFGINTERFACE27 (BASE_USBDEVICE+0X098) // ;cfg_interface register
#define USB_CFGINTERFACE28 (BASE_USBDEVICE+0X09c) // ;cfg_interface register
#define USB_CFGINTERFACE29 (BASE_USBDEVICE+0X0A0) // ;cfg_interface register
#define USB_CFGINTERFACE30 (BASE_USBDEVICE+0X0A4) // ;cfg_interface register
#define USB_CFGINTERFACE31 (BASE_USBDEVICE+0X0A8) // ;cfg_interface register
#define USB_PKTPASSEDCTRL (BASE_USBDEVICE+0X0AC) // ;@valid register aera
#define USB_PKTDROPPEDCTRL (BASE_USBDEVICE+0X0B0) // ;@valid register aera
#define USB_CRCERRCTRL (BASE_USBDEVICE+0X0B4) // ;@valid register aera
#define USB_BITSTUFFERRCTRL (BASE_USBDEVICE+0X0B8) // ;@valid register aera
#define USB_PIDERRCTRL (BASE_USBDEVICE+0X0BC) // ;@valid register aera
#define USB_FRAMINGERrCTRL (BASE_USBDEVICE+0X0C0) // ;@valid register aera
#define USB_TXPKTCTRL (BASE_USBDEVICE+0X0C4) // ;@valid register aera
#define USB_STATCTRLOV (BASE_USBDEVICE+0X0C8) // ;@valid register aera
#define USB_TXLENGTH (BASE_USBDEVICE+0X0CC)
#define USB_RXLENGTH (BASE_USBDEVICE+0X0D0)
#define USB_RESUME (BASE_USBDEVICE+0X0D4)
#define USB_READFLAG (BASE_USBDEVICE+0X0D8)
#define USB_RECEIVETYPE (BASE_USBDEVICE+0X0DC)
#define USB_APPLOCK (BASE_USBDEVICE+0X0E0)
#define USB_EP0OUTADDR (BASE_USBDEVICE+0X100)
#define USB_EP0OUTBMATTR (BASE_USBDEVICE+0X104)
#define USB_EP0OUTMAXPKTSIZE (BASE_USBDEVICE+0X108)
#define USB_EP0OUTIFNUM (BASE_USBDEVICE+0X10C)
#define USB_EP0OUTBMREQTYPE (BASE_USBDEVICE+0X114)
#define USB_EP0OUTBREQUEST (BASE_USBDEVICE+0X118)
#define USB_EP0OUTWVALUE (BASE_USBDEVICE+0X11C)
#define USB_EP0OUTWINDEX (BASE_USBDEVICE+0X120)
#define USB_EP0OUTWLENGTH (BASE_USBDEVICE+0X124)
#define USB_EP0OUTSYNCHFRAME (BASE_USBDEVICE+0X128)
#define USB_EP1INADDR (BASE_USBDEVICE+0X12C)
#define USB_EP1INBMATTR (BASE_USBDEVICE+0X130)
#define USB_EP1INMAXPKTSIZRE (BASE_USBDEVICE+0X134)
#define USB_EP1INIFNUM (BASE_USBDEVICE+0X138)
#define USB_EP1INSTAT (BASE_USBDEVICE+0x13C)
#define USB_EP1INBMREQTYPE (BASE_USBDEVICE+0X140)
#define USB_EP1INBREQUEST (BASE_USBDEVICE+0X144)
#define USB_EP1INWVALUE (BASE_USBDEVICE+0X148)
#define USB_EP1INWINDEX (BASE_USBDEVICE+0X14C)
#define USB_EP1INWLENGTH (BASE_USBDEVICE+0X150)
#define USB_EP1INSYNCHFRAME (BASE_USBDEVICE+0X154)
#define USB_EP1OUTADDR (BASE_USBDEVICE+0X158)
#define USB_EP1OUTBMATTR (BASE_USBDEVICE+0X15C)
#define USB_EP1OUTMAXPKTSIZE (BASE_USBDEVICE+0X160)
#define USB_EP1OUTIFNUM (BASE_USBDEVICE+0X164)
#define USB_EP1OUTSTAT (BASE_USBDEVICE+0X168)
#define USB_EP1OUTBMREQTYPE (BASE_USBDEVICE+0X16C)
#define USB_EP1OUTBREQUEST (BASE_USBDEVICE+0X170)
#define USB_EP1OUTWVALUE (BASE_USBDEVICE+0X174)
#define USB_EP1OUTWINDEX (BASE_USBDEVICE+0X178)
#define USB_EP1OUTWLENGTH (BASE_USBDEVICE+0X17C)
#define USB_EP1OUTSYNCHFRAME (BASE_USBDEVICE+0X180)
#define USB_EP2INADDR (BASE_USBDEVICE+0x2c+0X158)
#define USB_EP2INBMATTR (BASE_USBDEVICE+0x2c+0X15C)
#define USB_EP2INMAXPKTSIZE (BASE_USBDEVICE+0x2c+0X160)
#define USB_EP2INIFNUM (BASE_USBDEVICE+0x2c+0X164)
#define USB_EP2INSTAT (BASE_USBDEVICE+0x2c+0X168)
#define USB_EP2INBMREQTYPE (BASE_USBDEVICE+0x2c+0X16C)
#define USB_EP2INBREQUEST (BASE_USBDEVICE+0x2c+0X170)
#define USB_EP2INWVALUE (BASE_USBDEVICE+0x2c+0X174)
#define USB_EP2INWINDEX (BASE_USBDEVICE+0x2c+0X178)
#define USB_EP2INWLENGTH (BASE_USBDEVICE+0x2c+0X17C)
#define USB_EP2INSYNCHFRAME (BASE_USBDEVICE+0x2c+0X180)
#define USB_EP2OUTADDR (BASE_USBDEVICE+0x58+0X158)
#define USB_EP2OUTBMATTR (BASE_USBDEVICE+0x58+0X15C)
#define USB_EP2OUTMAXPKTSIZE (BASE_USBDEVICE+0x58+0X160)
#define USB_EP2OUTIFNUM (BASE_USBDEVICE+0x58+0X164)
#define USB_EP2OUTSTAT (BASE_USBDEVICE+0x58+0X168)
#define USB_EP2OUTBMREQTYPE (BASE_USBDEVICE+0x58+0X16C)
#define USB_EP2OUTBREQUEST (BASE_USBDEVICE+0x58+0X170)
#define USB_EP2OUTWVALUE (BASE_USBDEVICE+0x58+0X174)
#define USB_EP2OUTWINDEX (BASE_USBDEVICE+0x58+0X178)
#define USB_EP2OUTWLENGTH (BASE_USBDEVICE+0x58+0X17C)
#define USB_EP2OUTSYNCHFRAME (BASE_USBDEVICE+0x58+0X180)
#define USB_TXFIFO (BASE_USBDEVICE+0X300)
#define USB_RXFIFO (BASE_USBDEVICE+0X200)
/************************************
define PGIO registers
*************************************/
#define BASE_GPIO 0x1000B000
#define DBLK_DIV 0x1000b000
#define PORTA_DIR (BASE_GPIO + 0x04)
#define PORTA_SEL (BASE_GPIO + 0X08)
#define PORTA_DATA (BASE_GPIO + 0x0c)
#define PORTB_DIR (BASE_GPIO + 0x10)
#define PORTB_SEL (BASE_GPIO + 0X14)
#define PORTB_DATA (BASE_GPIO + 0x18)
#define PORTC_DIR (BASE_GPIO + 0x1C)
#define PORTC_SEL (BASE_GPIO + 0X20)
#define PORTC_DATA (BASE_GPIO + 0x24)
#define PORTD_DIR (BASE_GPIO + 0x28)
#define PORTD_SEL (BASE_GPIO + 0X2C)
#define PORTD_DATA (BASE_GPIO + 0x30)
#define PORTE_DIR (BASE_GPIO + 0x34)
#define PORTE_SEL (BASE_GPIO + 0X38)
#define PORTE_INCTL (BASE_GPIO + 0x3c)
#define PORTE_INTRCTL (BASE_GPIO + 0x40)
#define PORTE_INTRCLR (BASE_GPIO + 0x44)
#define PORTE_DATA (BASE_GPIO + 0x48)
#define PORTF_DIR (BASE_GPIO + 0x4C)
#define PORTF_SEL (BASE_GPIO + 0X50)
#define PORTF_DATA (BASE_GPIO + 0x54)
#define PORTG_DIR (BASE_GPIO + 0x58)
#define PORTG_SEL (BASE_GPIO + 0X5c)
#define PORTG_DATA (BASE_GPIO + 0x60)
#define PORTH_DIR (BASE_GPIO+0X68)
#define PORTH_SEL (BASE_GPIO+0X6c)
#define PORTH_INCTL (BASE_GPIO+0X70)
#define PORTH_INTRCTL (BASE_GPIO+0X74)
#define PORTH_INTRCLR (BASE_GPIO+0X78)
#define PORTH_DATA (BASE_GPIO+0X7c)
/************************************************
define PWM registers
************************************************/
#define BASE_PWM 0x1000c000
#define PWM1_TCTL (BASE_PWM + 0x00)
#define PWM1_TPRER (BASE_PWM + 0x04)
#define PWM1_TCMP (BASE_PWM + 0x08)
#define PWM1_TCR (BASE_PWM + 0x0C)
#define PWM2_TCTL (BASE_PWM + 0x10)
#define PWM2_TPRER (BASE_PWM + 0x14)
#define PWM2_TCMP (BASE_PWM + 0x18)
#define PWM2_TCR (BASE_PWM + 0x1c)
/**************************************
define EMI registers
****************************************/
#define BASE_EMI 0x11000000
#define EMI_SMCON ( BASE_EMI + 0x00 )
#define EMI_CSGBAB ( BASE_EMI + 0x04 )
#define EMI_CSGBCD ( BASE_EMI + 0x08 )
#define EMI_CSGBEF ( BASE_EMI + 0x0c )
#define EMI_REMAP ( BASE_EMI + 0x10 )
#define EMI_SDCONF1 ( BASE_EMI + 0x14 )
#define EMI_SDCONF2 ( BASE_EMI + 0x18 )
#define EMI_REMAP2EMI ( BASE_EMI + 0x1c )
#define EMI_NAND_ADDR ( BASE_EMI + 0x100 )
#define EMI_NAND_COM ( BASE_EMI + 0x104 )
#define EMI_NAND_STATUS ( BASE_EMI + 0x10c )
#define EMI_ERROR_ADDR1 ( BASE_EMI + 0x110 )
#define EMI_ERROR_ADDR2 ( BASE_EMI + 0x114 )
#define EMI_NAND_CONF ( BASE_EMI + 0x118 )
#define EMI_NANDINTR ( BASE_EMI + 0x11c )
#define EMI_NANDFINECC ( BASE_EMI + 0x120 )
#define EMI_NANDIDLE ( BASE_EMI + 0x124 )
#define EMI_NAND_DATA ( BASE_EMI + 0x200 )
/****************************************
define DMA registers
****************************************/
#define BASE_DMA 0x11001000
#define DMAC_IntStatus (BASE_DMA+0x20)
#define DMAC_IntTCStatus (BASE_DMA+0x50)
#define DMAC_IntTCClear (BASE_DMA+0x60)
#define DMAC_RawIntTCStatus (BASE_DMA+0x70)
#define DMAC_IntErrorStatus (BASE_DMA+0x80)
#define DMAC_IntErrClr (BASE_DMA+0x90)
#define DMAC_RawIntErrorStatus (BASE_DMA+0xa0)
#define DMAC_EnbldChns (BASE_DMA+0xB0)
#define DMAC0_SrcAddr (BASE_DMA+0x1000)
#define DMAC0_DestAddr (BASE_DMA+0x1004)
#define DMAC0_Control (BASE_DMA+0x100c)
#define DMAC0_Configuration (BASE_DMA+0x1010)
#define DMAC1_SrcAddr (BASE_DMA+0x1100)
#define DMAC1_DestAddr (BASE_DMA+0x1104)
#define DMAC1_Control (BASE_DMA+0x110c)
#define DMAC1_Configuration (BASE_DMA+0x1110)
#define DMAC2_SrcAddr (BASE_DMA+0x1200)
#define DMAC2_DestAddr (BASE_DMA+0x1204)
#define DMAC2_Control (BASE_DMA+0x120c)
#define DMAC2_Configuration (BASE_DMA+0x1210)
#define DMAC3_SrcAddr (BASE_DMA+0x1300)
#define DMAC3_DestAddr (BASE_DMA+0x1304)
#define DMAC3_Control (BASE_DMA+0x130c)
#define DMAC3_Configuration (BASE_DMA+0x1310)
#define DMAC4_SrcAddr (BASE_DMA+0x1400)
#define DMAC4_DestAddr (BASE_DMA+0x1404)
#define DMAC4_Control (BASE_DMA+0x140c)
#define DMAC4_Configuration (BASE_DMA+0x1410)
#define DMAC5_SrcAddr (BASE_DMA+0x1500)
#define DMAC5_DestAddr (BASE_DMA+0x1504)
#define DMAC5_Control (BASE_DMA+0x150c)
#define DMAC5_Configuration (BASE_DMA+0x1510)
/*************************************
define LCDC registers
*************************************/
#define BASE_LCDC 0x11002000
#define LCDC_SSA (BASE_LCDC+0x00)
#define LCDC_SIZE (BASE_LCDC+0x04)
#define LCDC_PCR (BASE_LCDC+0x08)
#define LCDC_HCR (BASE_LCDC+0x0c)
#define LCDC_VCR (BASE_LCDC+0x10)
#define LCDC_PWMR (BASE_LCDC+0x14)
#define LCDC_LECR (BASE_LCDC+0x18)
#define LCDC_DMACR (BASE_LCDC+0x1c)
#define LCDC_LCDICR (BASE_LCDC+0x20)
#define LCDC_LCDISR (BASE_LCDC+0x24)
#define LCDC_LGPMR (BASE_LCDC+0x40)
/*************************************
define MMA registers
*************************************/
#define BASE_MMA 0x11003000
#define MMA_MODER ( BASE_MMA + 0xff0)
#define MMA_STAUTS ( BASE_MMA + 0xff4 )
#define MMA_BUFXAR ( BASE_MMA + 0xff8 )
#define MMA_BUFZAR ( BASE_MMA + 0xffc )
#define MMA_SRAM_Base ( BASE_MMA + 0x00 )
#endif
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