📄 gfd_reg.h
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/*************************************************************
Copyright (c) 2006, 南京博芯电子有限公司研发部
All rights reserved.
文件名称: GFD_reg.h
摘 要: 定义SEP3203内部寄存器地址
当前版本 : 1.0
作 者 : Darrell Zheng
完成日期: 2006.4.3.
修改记录:
Ver Date Author Comments
--------------------------------------------------------------
1.0 2006.4.3 Darrell Creat this file
**************************************************************/
#ifndef _HARWARE_REG_H
#define _HARWARE_REG_H
//#include "TypeDef.h"
//#include "config.h"
/***************************************************
define INTC registers
***************************************************/
#define BASE_INTC (0x10000000)
#define INTC_IEN ( BASE_INTC+0X0 )
#define INTC_IMSK ( BASE_INTC+0X8 )
#define INTC_IFCE ( BASE_INTC+0X10 )
#define INTC_IRSTAT ( BASE_INTC+0X18 )
#define INTC_ISTAT ( BASE_INTC+0X20 )
#define INTC_IMSTAT ( BASE_INTC+0X28 )
#define INTC_IFSTAT ( BASE_INTC+0X30 )
#define INTC_FEN ( BASE_INTC+0XC0 )
#define INTC_FMSK ( BASE_INTC+0XC4 )
#define INTC_FFCE ( BASE_INTC+0XC8 )
#define INTC_FRSTAT ( BASE_INTC+0XCC )
#define INTC_FSTAT ( BASE_INTC+0XD0 )
#define INTC_FFSTAT ( BASE_INTC+0XD4 )
#define INTC_PLV ( BASE_INTC+0XD8 )
/* definition of register address */
#define TIMER_BASE 0X10003000
#define T1_LCR (TIMER_BASE+0X00)
#define T1_CCR (TIMER_BASE+0X04)
#define T1_CR (TIMER_BASE+0X08)
#define T1_ISCR (TIMER_BASE+0X0C)
#define T1_IMSR (TIMER_BASE+0X10)
#define T2_LCR (TIMER_BASE+0X14)
#define T2_CCR (TIMER_BASE+0X18)
#define T2_CR (TIMER_BASE+0X1C)
#define T2_ISCR (TIMER_BASE+0X20)
#define T2_IMSR (TIMER_BASE+0X24)
#define T3_LCR (TIMER_BASE+0X28)
#define T3_CCR (TIMER_BASE+0X2C)
#define T3_CR (TIMER_BASE+0X30)
#define T3_ISCR (TIMER_BASE+0X34)
#define T3_IMSR (TIMER_BASE+0X38)
#define T4_LCR (TIMER_BASE+0X3C)
#define T4_CCR (TIMER_BASE+0X40)
#define T4_CR (TIMER_BASE+0X44)
#define T4_ISCR (TIMER_BASE+0X48)
#define T4_IMSR (TIMER_BASE+0X4C)
/*************************************************
define PMU registers
*************************************************/
#define PMU_BASE 0x10001000
#define PMU_PLTR (PMU_BASE+0X00)
#define PMU_PMCR (PMU_BASE+0X04)
#define PMU_PUCR (PMU_BASE+0X08)
#define PMU_PCSR (PMU_BASE+0X0C)
#define PMU_PMDR (PMU_BASE+0X14)
/*************************************************
defien RTC registers
*************************************************/
#define RTC_BASE 0x10002000
#define RTC_YMD (RTC_BASE + 0X00) //year ,month ,day regment
#define RTC_HMS (RTC_BASE + 0X04) //hour ,minute ,second regment
#define RTC_ALRM (RTC_BASE + 0X08) //alarm time regment
#define RTC_CTRL (RTC_BASE + 0X0c) //rtc control regment
#define RTC_IEN (RTC_BASE + 0X10) //interrupt enable regment
#define RTC_ISTAT (RTC_BASE + 0X14) //interrupt status regment
#define RTC_SAMP (RTC_BASE + 0X18) //sample regment
#define RTC_WCNT (RTC_BASE + 0X1c) //watchdog count regment
#define RTC_WSVCE (RTC_BASE + 0X20) //Watchdog service regment
/*************************************************
define GPT registers
*************************************************/
#define GPT_BASE 0x10003000
#define GPT1_LCR (GPT_BASE + 0x00)
#define GPT1_CCR (GPT_BASE + 0x04)
#define GPT1_CR (GPT_BASE + 0x08)
#define GPT1_ISCR (GPT_BASE + 0x0c)
#define GPT1_IMSR (GPT_BASE + 0x10)
#define GPT2_LCR (GPT_BASE + 0x14)
#define GPT2_CCR (GPT_BASE + 0x18)
#define GPT2_CR (GPT_BASE + 0x1c)
#define GPT2_ISCR (GPT_BASE + 0x20)
#define GPT2_IMSR (GPT_BASE + 0x24)
#define GPT3_LCR (GPT_BASE + 0x28)
#define GPT3_CCR (GPT_BASE + 0x2c)
#define GPT3_CR (GPT_BASE + 0x30)
#define GPT3_ISCR (GPT_BASE + 0x34)
#define GPT3_IMSR (GPT_BASE + 0x38)
#define GPT4_LCR (GPT_BASE + 0x3c)
#define GPT4_CCR (GPT_BASE + 0x40)
#define GPT4_CR (GPT_BASE + 0x44)
#define GPT4_ISCR (GPT_BASE + 0x48)
#define GPT4_IMSR (GPT_BASE + 0x4c)
#define GPT_TIMSR (GPT_BASE + 0xa0)
#define GPT_TISCR (GPT_BASE + 0xa4)
#define GPT_TISR (GPT_BASE + 0xa8)
/*********************************************
define UART registers
*********************************************/
#define BASE_UART0 0x10004000
#define BASE_UART1 0x10005000
#define UART0_THR (BASE_UART0+0x00)
#define UART0_RBR (BASE_UART0+0x00)
#define UART0_DLL (BASE_UART0+0x00)
#define UART0_DLH (BASE_UART0+0x04)
#define UART0_IER (BASE_UART0+0x04)
#define UART0_IIR (BASE_UART0+0x08)
#define UART0_FCR (BASE_UART0+0x08)
#define UART0_LCR (BASE_UART0+0x0c)
#define UART0_MCR (BASE_UART0+0x10)
#define UART0_LSR (BASE_UART0+0x14)
#define UART0_MSR (BASE_UART0+0x18)
#define UART1_THR (BASE_UART1+0x00)
#define UART1_RBR (BASE_UART1+0x00)
#define UART1_DLL (BASE_UART1+0x00)
#define UART1_DLH (BASE_UART1+0x04)
#define UART1_IER (BASE_UART1+0x04)
#define UART1_IIR (BASE_UART1+0x08)
#define UART1_FCR (BASE_UART1+0x08)
#define UART1_LCR (BASE_UART1+0x0c)
#define UART1_MCR (BASE_UART1+0x10)
#define UART1_LSR (BASE_UART1+0x14)
#define UART1_MSR (BASE_UART1+0x18)
/**************************************
define SPI registers
****************************************/
#define BASE_SPI 0x10006000
#define SPI_CR (BASE_SPI + 0X00)
#define SPI_BR (BASE_SPI + 0X04)
#define SPI_SR (BASE_SPI + 0X08)
#define SPI_TR (BASE_SPI + 0X0C)
#define SPI_RR (BASE_SPI + 0x10)
#define SPI_ICSR (BASE_SPI + 0x14)
/************************************************
define AC97 registers
************************************************/
#define BASE_AC97 0x10008000
#define AC97_CONR (BASE_AC97+0X00) //AC97 control register
#define AC97_OCR (BASE_AC97+0X04) //Output Channel Configure Register
#define AC97_ICR (BASE_AC97+0X08) //Input Channel Configure Register
#define AC97_CRAC (BASE_AC97+0X0c) //codec register access register
#define AC97_INT_ENABLE (BASE_AC97+0X10)
#define AC97_INT_STATUS (BASE_AC97+0X14)
#define AC97_INT_CLEAR (BASE_AC97+0X18)
#define AC97_ENABLE (BASE_AC97+0X1c)
#define AC97_OUT_FIFOADDR (BASE_AC97+0X20)
#define AC97_MONO_FIFOADDR (BASE_AC97+0X30)
/**************************************
define MMC registers
****************************************/
#define BASE_MMCC 0X10009000
#define MMCC_STR_STP_CLK (BASE_MMCC+0x00)
#define MMCC_STATUS (BASE_MMCC+0X04)
#define MMCC_CLK_RATE (BASE_MMCC+0X08)
#define MMCC_CMD_DAT_CONT (BASE_MMCC+0X0C)
#define MMCC_RES_TO (BASE_MMCC+0X10)
#define MMCC_READ_TO (BASE_MMCC+0X14)
#define MMCC_BLK_LEN (BASE_MMCC+0X18)
#define MMCC_NOB (BASE_MMCC+0X1C)
#define MMCC_DAT_COUNT (BASE_MMCC+0X20)
#define MMCC_INT_MASK (BASE_MMCC+0X24)
#define MMCC_CMD (BASE_MMCC+0X28)
#define MMCC_ARG (BASE_MMCC+0X2C)
#define MMCC_RESPONSE0 (BASE_MMCC+0X30)
#define MMCC_RESPONSE1 (BASE_MMCC+0X34)
#define MMCC_RESPONSE2 (BASE_MMCC+0X38)
#define MMCC_RESPONSE3 (BASE_MMCC+0X3C)
#define MMCC_WRITE_BUFER_ACCESS (BASE_MMCC+0X40)
#define MMCC_READ_BUFER_ACCESS (BASE_MMCC+0X44)
/**************************************
define USBregisters
****************************************/
#define BASE_USBDEVICE 0x1000a000 //BASE ADDRESS OF usb device
#define USB_INTR (BASE_USBDEVICE+0X000) // ;int register
#define USB_INTRMASK (BASE_USBDEVICE+0X004) // ;imask register
#define USB_INTRCTRL (BASE_USBDEVICE+0X008) // ;control register
#define USB_EPINFO (BASE_USBDEVICE+0X00c) // ;information register
#define USB_BCONFIGURATIONVALUE (BASE_USBDEVICE+0X010) // ;configuration of value register
#define USB_BMATTRIBUTES (BASE_USBDEVICE+0X014) // ;configuration of bmattr register
#define USB_DEVSPEED (BASE_USBDEVICE+0X018) // ;record status register
#define USB_FRAMENUMBER (BASE_USBDEVICE+0X01C) // ;record status register
#define USB_EPTRANSACTIONS0 (BASE_USBDEVICE+0X020) // ;record status register
#define USB_EPTRANSACTIONS1 (BASE_USBDEVICE+0X024) // ;record status register
#define USB_APPIFUPDATE (BASE_USBDEVICE+0X028) // ;record status register
#define USB_CFGINTERFACE0 (BASE_USBDEVICE+0X02C) // ;cfg_interface register
#define USB_CFGINTERFACE1 (BASE_USBDEVICE+0X030) // ;cfg_interface register
#define USB_CFGINTERFACE2 (BASE_USBDEVICE+0X034) // ;cfg_interface register
#define USB_CFGINTERFACE3 (BASE_USBDEVICE+0X038) // ;cfg_interface register
#define USB_CFGINTERFACE4 (BASE_USBDEVICE+0X03c) // ;cfg_interface register
#define USB_CFGINTERFACE5 (BASE_USBDEVICE+0X040) // ;cfg_interface register
#define USB_CFGINTERFACE6 (BASE_USBDEVICE+0X044) // ;cfg_interface register
#define USB_CFGINTERFACE7 (BASE_USBDEVICE+0X048) // ;cfg_interface register
#define USB_CFGINTERFACE8 (BASE_USBDEVICE+0X04c) // ;cfg_interface register
#define USB_CFGINTERFACE9 (BASE_USBDEVICE+0X050) // ;cfg_interface register
#define USB_CFGINTERFACE10 (BASE_USBDEVICE+0X054) // ;cfg_interface register
#define USB_CFGINTERFACE11 (BASE_USBDEVICE+0X058) // ;cfg_interface register
#define USB_CFGINTERFACE12 (BASE_USBDEVICE+0X05c) // ;cfg_interface register
#define USB_CFGINTERFACE13 (BASE_USBDEVICE+0X060) // ;cfg_interface register
#define USB_CFGINTERFACE14 (BASE_USBDEVICE+0X064) // ;cfg_interface register
#define USB_CFGINTERFACE15 (BASE_USBDEVICE+0X068) // ;cfg_interface register
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