sdk7a400_board.h

来自「Sharp LH7A400 BSP平台无关部分的代码,有很高的参考价值,尤其是系」· C头文件 代码 · 共 497 行 · 第 1/2 页

/***********************************************************************
 * Interrupt/mask register and bits
 *  Bit 0 = read only
 *    0 = LAN interrupt pending
 *    1 = LAN interrupt NOT pending
 *  Bit 1 = read only
 *    0 = Touchscreen interrupt pending
 *    1 = Touchscreen interrupt NOT pending
 *  Bit 2 = read/write
 *    0 = LAN interrupt is enabled
 *    1 = LAN interrupt is masked
 *  Bit 3 = read/write
 *    0 = Touchscreen interrupt is enabled
 *    1 = Touchscreen interrupt is masked
 *  Bit 4 = read/write
 *    0 = Pen interrupt is output
 *    1 = Pen interrupt is input
 *  Bit 5 = not used
 *  Bit 6 = read only
 *    0 = CPLD interrupt is pending
 *    1 = CPLD interrupt is not pending
 *  Bit 7 = read/write
 *    0 = Pen interrupt is output
 *    1 = Pen interrupt is input
 **********************************************************************/

/* Interrupt/mask register address */
#define INTMSK_REG_BASE         (CPLD_FAST_BASE + 0x00C00000)

/* Interrupt/mask LAN interrupt pending bit */
#define INTMSK_LAN_PENDING      0x0001

/* Interrupt/mask Touchscreen interrupt pending bit */
#define INTMSK_TS_PENDING       0x0002

/* Interrupt/mask LAN interrupt disable bit */
#define INTMSK_LAN_DISABLE      0x0004

/* Interrupt/mask Touchscreen interrupt disable bit */
#define INTMSK_TS_DISABLE       0x0008

/* PEN interrupt configured as input bit */
#define INTMSK_PENIRQ_IN        0x0010

/* CPLD interrupt pending bit */
#define INTMSK_CPLD_PENDING     0x0040

/* CPLD interrupt enable bit */
#define INTMSK_CPLD_ENABLE      0x0080

/***********************************************************************
 * Mode register and bits
 *  Bits 0..1 = read only
 *    01 = 8-bit boot bus width
 *    10 = 16-bit boot bus width
 *    11 = 32-bit boot bus width
 *  Bit 2 = read only (ignored on the LH7A400, little endian only)
 *    0 = Big endian operation
 *    1 = Little endian operation
 *  Bit 3 = read only
 *    0 = Boot device was an external device
 *    1 = Boot device was an internal device
 *  Bit 4 = read only
 *    0 = PCMCIA card detect 1 is low
 *    1 = PCMCIA card detect 1 is high
 *  Bit 5 = read only
 *    0 = PCMCIA IOIS16 interrupt is enabled
 *    1 = PCMCIA IOIS16 interrupt is not enabled
 *  Bit 6 = read only
 *    0 = PCMCIA card detect 2 is low
 *    1 = PCMCIA card detect 2 is high
 *  Bit 7 = read only
 *    0 = PCMCIA voltage sense 1 is low
 *    1 = PCMCIA voltage sense 1 is high
 **********************************************************************/

/* Mode register address */
#define MODE_REG_BASE           (CPLD_FAST_BASE + 0x00E00000)

/* Mode register, bus width is 8-bits value */
#define MODE_BUS_8_WIDTH        0x0001

/* Mode register, bus width is 16-bits value */
#define MODE_BUS_16_WIDTH       0x0002

/* Mode register, bus width is 32-bits value */
#define MODE_BUS_32_WIDTH       0x0003

/* Mode register, bus width value mask */
#define MODE_BUS_WIDTH_MASK     0x0003

/* Mode register little endian mask bit */
#define MODE_LITTLE_ENDIAN      0x0004

/* Mode register boot device internal mask bit */
#define MODE_BOOTDEV_INT        0x0008

/* Mode register PCMCIA card detect 1 mask bit */
#define MODE_PCC_CD1_MASK       0x0010
                         
/* Mode register IOIS16 interrupt enable bit */
#define MODE_PCCIOIS16_ENABLE   0x0020

/* Mode register PCMCIA card detect 2 mask bit */
#define MODE_PCC_CD2_MASK       0x0040

/* Mode register PCMCIA voltage sense 1 mask bit */
#define MODE_PCC_VS1_MASK       0x0080

/***********************************************************************
 * Flash register and bits
 *  Bit 0 = read/write
 *    0 = Normal FLASH operation
 *    1 = Allow FLASH programming
 *  Bit 1 = read only
 *    Returns state of FLASH_STS1 signal
 *  Bit 2 = read only
 *    Returns state of FLASH_STS2 signal
 *  Bit 3 = read/write
 *    0 = FLASH populated
 *    1 = No FLASH populated
 **********************************************************************/

/* Flash register address */
#define FLASH_REG_BASE          (CPLD_FAST_BASE + 0x01000000)

/* Flash register enable programming bit */
#define FLASH_PROG_ENABLE       0x0001

/* Flash register STS1 mask bit */
#define FLASH_STS1_MASK         0x0002

/* Flash register STS2 mask bit */
#define FLASH_STS2_MASK         0x0004

/* Flash register populated bit */
#define FLASH_POP_BIT           0x0008

/***********************************************************************
 * Power management register and bits
 *  Bit 2 = read only returns state of suspend signal
 *  Bit 4 = read only returns state of standby signal
 **********************************************************************/

/* Power management register address */
#define PWMAN_REG_BASE          (CPLD_FAST_BASE + 0x01200000)

/* Power management register suspend signal bit mask */
#define PWMAN_SUSPEND_BIT       0x0004

/* Power management register suspend signal bit mask */
#define PWMAN_STANDBY_BIT       0x0010

/***********************************************************************
 * CPLD revision register and bits
 *  Bits 0..7 = read only returns 8-bit CPLD revision code
 **********************************************************************/

/* CPLD revision register address */
#define CPREV_REG_BASE          (CPLD_FAST_BASE + 0x01400000)

/***********************************************************************
 * LED register and bits
 *  Bit 0 = read/write
 *    0 = Turn GPIO app board LED on
 *    1 = Turn GPIO app board LED off
 *  Bit 1 = read/write
 *    0 = Turn status2 app board LED on
 *    1 = Turn status2 app board LED off
 *  Bit 2 = read/write
 *    0 = Turn status1 app board LED on
 *    1 = Turn status1 app board LED off
 **********************************************************************/

/* LED register address */
#define LED_REG_BASE            (CPLD_FAST_BASE + 0x01600000)

/* LED register GPIO app board LED disable bit (status2) */
#define LED_GPIO_DISABLE        0x0001

/* LED register GPIO app board LED disable bit (status2) */
#define LED_STATUS2_DISABLE     0x0002

/* LED register GPIO app board LED disable bit (status1) */
#define LED_STATUS1_DISABLE     0x0004

/***********************************************************************
 * GPIO data register and bits
 *  Bits 0 = read/write of GPIO data value for bit 0
 **********************************************************************/

/* GPIO data register address - reading this 8-bit register returns the
   value of signal CPLD_GPIO_2 on bit 0 */
#define GPDAT_REG_BASE          (CPLD_FAST_BASE + 0x01800000)

/***********************************************************************
 * GPIO data direction register and bits
 *  Bit 0 = read/write
 *    0 = GPIO data register is an input
 *    1 = GPIO data register is an output
 **********************************************************************/

/* GPIO data direction register address */
#define GPDIR_REG_BASE          (CPLD_FAST_BASE + 0x01A00000)

/* GPIO data register bit 2 is an input */
#define GPDIR_INPUT_CPLD2_SEL   0x0001

/***********************************************************************
 * SDRAM interface specific defines
 **********************************************************************/

#define SDRAM1_SEG1_ADDR  0xC0000000   /* SDRAM 1 segment 1 address */
#define SDRAM1_SEG2_ADDR  0xC1000000   /* SDRAM 1 segment 2 address */
#define SDRAM1_SEG3_ADDR  0xC4000000   /* SDRAM 1 segment 3 address */
#define SDRAM1_SEG4_ADDR  0xC5000000   /* SDRAM 1 segment 4 address */
#define SDRAM1_SEG5_ADDR  0xC8000000   /* SDRAM 1 segment 5 address */
#define SDRAM1_SEG6_ADDR  0xC9000000   /* SDRAM 1 segment 6 address */
#define SDRAM1_SEG7_ADDR  0xCC000000   /* SDRAM 1 segment 7 address */
#define SDRAM1_SEG8_ADDR  0xCD000000   /* SDRAM 1 segment 8 address */
                         
/* The following SDRAM segments are only available on 64MByte card
   engines */
#define SDRAM2_SEG1_ADDR  0xD0000000   /* SDRAM 2 segment 1 address */
#define SDRAM2_SEG2_ADDR  0xD1000000   /* SDRAM 2 segment 2 address */
#define SDRAM2_SEG3_ADDR  0xD4000000   /* SDRAM 2 segment 3 address */
#define SDRAM2_SEG4_ADDR  0xD5000000   /* SDRAM 2 segment 4 address */
#define SDRAM2_SEG5_ADDR  0xD8000000   /* SDRAM 2 segment 5 address */
#define SDRAM2_SEG6_ADDR  0xD9000000   /* SDRAM 2 segment 6 address */
#define SDRAM2_SEG7_ADDR  0xDC000000   /* SDRAM 2 segment 7 address */
#define SDRAM2_SEG8_ADDR  0xDD000000   /* SDRAM 2 segment 8 address */

/* Size of an SDRAM segment, 16 segments total */
#define SDRAM_SEG_SIZE    (4 * 1024 * 1024)

/* SDRAM chip select 0/1 configuration values */
#define SDRAM_CS_CONFIG (SDRAM_NSDCS_RASTOCAS_RASL2 | \
    SDRAM_NSDCS_CASLAT3 | SDRAM_NSDCS_BANKCOUNT4 | SDRAM_NSDCS_EBW32)

/* SDRAM mode word for burst size of 4 words, non-interleaved, CAS3 */
#define SDRAM_MODE_WORD   0x32

/* Refresh interval reciprocal value used to determine optimal refresh
   value (64000 = 1 / 15.625uS) */
#define SDRAM_REFRESH_INTERVAL 64000

#endif /* SDK7A400_BOARD_H */