sdk7a400_board.h

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/***********************************************************************
 * $Workfile:   sdk7a400_board.h  $
 * $Revision:   1.3  $
 * $Author:   WellsK  $
 * $Date:   Mar 18 2004 10:50:50  $
 *
 * Project: LogicPD SDK7A400 board definitions
 *
 * Description:
 *     This file contains board specific information such as the
 *     chip select wait states, and other board specific information.
 *
 * Revision History:
 * $Log:   //smaicnt2/pvcs/VM/sharpmcu/archives/sharpmcu/software/csps/lh7a400/bsps/sdk7a400/include/sdk7a400_board.h-arc  $
 * 
 *    Rev 1.3   Mar 18 2004 10:50:50   WellsK
 * Various corrections for bus wait states. Added support for rev.
 * B card engines. Added a card engine version selection flag.
 * 
 *    Rev 1.2   Aug 12 2003 14:25:28   WellsK
 * Corrected bitfields and polarity on some CPLD registers.
 * Added 64MByte SDRAM support and changed CAS latency
 * to 3 clocks from 2 clocks.
 * 
 *    Rev 1.1   Jul 02 2003 17:55:34   WellsK
 * Removed lots of unused defines not applicable to this board.
 * 
 *    Rev 1.0   Jun 19 2003 11:04:14   WellsK
 * Initial revision.
 *
 *
 ***********************************************************************
 * SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION
 * OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE,
 * AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES, 
 * SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE.
 *
 * SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY 
 * FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A 
 * SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT. USE OF THIS SOURCE
 * FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS.
 *
 * COPYRIGHT (C) 2001 SHARP MICROELECTRONICS OF THE AMERICAS, INC.
 *     CAMAS, WA
 **********************************************************************/
#ifndef SDK7A400_BOARD_H
#define SDK7A400_BOARD_H

#include "abl_types.h"
#include "lh7a400_smc.h"
#include "lh7a400_sdramc.h"
#include "lh7a400_chip.h"

/***********************************************************************
 * Board or verions specific defines - these need to be customized
 * based on the product for which this is being compiled.
 **********************************************************************/

/* If the card has 64MBytes of memory, enable the SDRAM64 define. If
   this is used, the startup code assumes that 32MBytes of SDRAM is
   on chip select 0 and the other 32MBytes are on chip select 1. */
#undef SDRAM64

/* The following define is used to control how some sections of code
   are compiled for different versions of the LH7A400 card engine.
   This must match the version of the card engine that is being used
   with this code. At present, card engines version A01 (1) and
   B01 (2) are used. */
//#define CEVERSION 1       /* Use A01 card engine */
#define CEVERSION 2       /* Use B01 card engine */

/***********************************************************************
 * Chip select configurations (per LogicPD)
 **********************************************************************/

/* Static Memory Controller chip select 0 load value for FLASH */
#define SMC_BCR0_INIT   (SMC_BCR_MW32 | SMC_BCR_WST2(0) | \
                         SMC_BCR_WST1(14) | SMC_BCR_IDCY(0)) 

/* Static Memory Controller chip selects 1, 2, and 3 are not used */

/* Static Memory Controller chip selects 4 through 5 are used for
   the SDK7A400 PC Card slots and will be setup later */

/* Static Memory Controller chip select 6 load value for slow CPLD
   peripherals */
#define SMC_BCR6_INIT   (SMC_BCR_MW16 | SMC_BCR_WST2(0)| \
                         SMC_BCR_WST1(31) | SMC_BCR_IDCY(0))

/* Static Memory Controller chip select 7 load value for fast CPLD
   peripherals */
#define SMC_BCR7_INIT   (SMC_BCR_MW16 | SMC_BCR_WST2(0) |  \
                         SMC_BCR_WST1(22)| SMC_BCR_IDCY(2))

/***********************************************************************
 * CPLD register addresses - slow CPLD base
 **********************************************************************/

/* Base address of slow CPLD registers and remapping selects */
#define CPLD_SLOW_BASE          SMC_CS6_BASE

/* CompactFlash (memory mode)(chip select) device base address */
#define CF_BASE                 (CPLD_SLOW_BASE + 0x00200000)

/* ISA/EISA IO (chip select) base address */
#define EISA_BASE               (CPLD_SLOW_BASE + 0x00400000)

/***********************************************************************
 * CPLD register addresses - fast CPLD base
 **********************************************************************/

/* Base address of fast CPLD registers and remapping selects */
#define CPLD_FAST_BASE          SMC_CS7_BASE

/* LAN device (chip select) base address */
#define LAN_BASE                (CPLD_FAST_BASE + 0x00000000)

/***********************************************************************
 * Card engine general control register and bits
 *  Bit 0 = read/write
 *    0 = LAN power enabled
 *    1 = LAN power disabled
 *  Bit 1 = read/write
 *    0 = Set LCD_VEEEN to 0
 *    1 = Set LCD_VEEEN to 1
 *  Bit 2 = read/write
 *    0 = Auto-wakeup enabled
 *    1 = Auto-wakeup disabled
 *  Bit 3 = read/write
 *    0 = USB power 1 enabled
 *    1 = USB power 1 disabled
 *  Bit 4 = read only
 *    0 = USB connection 1 interrupt active
 *    1 = USB connection 1 interrupt not active
 *  Bit 5 = read/write
 *    0 = PCC_nDRIVE output is active
 *    1 = PCC_nDRIVE output is not active
 *  Bit 6 = read/write
 *    0 = USB connection 1 interrupt is not masked
 *    1 = USB connection 1 interrupt is masked
 *  Bit 7 = read/write
 *    0 = Generate a software interrupt via the CPLD
 *    1 = Do not generate a software interrupt via the CPLD
 **********************************************************************/

/* Card engine general control register address */
#define CARDE_REG_BASE          (CPLD_FAST_BASE + 0x00200000)

/* Card engine LAN power disable bit */
#define CARDE_LAN_PWR_DISABLE   0x0001

/* Card engine LCD_VEEEN enable bit */
#define CARDE_VEEEN_ENABLE      0x0002

/* Card engine auto-wakeup enable bit */
#define CARDE_AUTOW_ENABLE      0x0004

/* Card engine USB 1 power enable bit */
#define CARDE_USB1PWR_ENABLE    0x0008

/* Card engine USB 1 connection interrupt pending bit */
#define CARDE_USB1INT_PENDING   0x0010

/* Card engine PCC_nDRIVE activate bit */
#define CARDE_PCCNDRIVE_ENABLE  0x0020

/* Card engine USB connection 1 interrupt enable bit */
#define CARDE_USB1INT_ENABLE    0x0040

/* Card engine CPLD software interrupt bit */
#define CARDE_CPLDINT_GEN       0x0080

/***********************************************************************
 * SPI data register and bits
 *  Bits 0..7 = read/write of SPI data
 **********************************************************************/

/* SPI data register address */
#define SPIDAT_REG_BASE         (CPLD_FAST_BASE + 0x00600000)

/* SPI data register load macro */
#define SPIDAT_DATA(n)          ((n) & 0x00FF)

/***********************************************************************
 * SPI control register and bits
 *  Bit 0 = read/write (not used on SDK7A400)
 *    0 = Deselect CODEC for SPI
 *    1 = Select CODEC for SPI
 *  Bit 1 = read/write
 *    0 = Deselect touchscreen for SPI
 *    1 = Select touchscreen for SPI
 *  Bit 2 = read/write
 *    0 = Write SPI data
 *    1 = Read SPI data
 *  Bit 3 = read only
 *    0 = SPI access NOT done
 *    1 = SPI access complete
 *  Bit 4 = read/write
 *    0 = Don't load SPI register and reset shift count
 *    1 = Ready to load SPI register and reset shift count
 *  Bit 5 = read only
 *    0 = SPI register has not been loaded
 *    1 = SPI register has been loaded
 **********************************************************************/

/* SPI control register address */
#define SPICON_REG_BASE         (CPLD_FAST_BASE + 0x00800000)

/* SPI control register CODEC selection bit (not used) */
#define SPICON_CODEC_SEL        0x0001

/* SPI control register touchscreen selection bit */
#define SPICON_TOUCH_SEL        0x0002

/* SPI control register read/write selection bit */
#define SPICON_READ_SEL         0x0004

/* SPI control register access complete selection bit */
#define SPICON_ACCESS_DONE      0x0008

/* SPI control register start load selection bit */
#define SPICON_START            0x0010

/* SPI control register load complete selection bit */
#define SPICON_LOAD_DONE        0x0020

/***********************************************************************
 * EEPROM SPI register and bits
 *  Bit 0 = read only of SPI data bit (RX)
 *  Bit 1 = read/write of SPI data (TX)
 *  Bit 2 = read/write of SPI clock
 *  Bit 3 = read/write of EEPROM chip select
 **********************************************************************/

/* EEPROM SPI register address */
#define EE2SPI_REG_BASE         (CPLD_FAST_BASE + 0x00A00000)

/* EEPROM SPI RX data bit */
#define EE2SPI_RXDAT            0x0001

/* EEPROM SPI TX data bit */
#define EE2SPI_TXDAT            0x0002

/* EEPROM SPI clock data bit */
#define EE2SPI_CLK              0x0004

/* EEPROM SPI chip select data bit */
#define EE2SPI_CS               0x0008