📄 gyb.mdl
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Model { Name "gyb" Version 5.1 SaveDefaultBlockParams on SampleTimeColors off LibraryLinkDisplay "none" WideLines off ShowLineDimensions off ShowPortDataTypes off ShowLoopsOnError on IgnoreBidirectionalLines off ShowStorageClass off SortedOrder off RecordCoverage off CovPath "/" CovSaveName "covdata" CovMetricSettings "dw" CovNameIncrementing off CovHtmlReporting on covSaveCumulativeToWorkspaceVar on CovSaveSingleToWorkspaceVar on CovCumulativeVarName "covCumulativeData" CovCumulativeReport off DataTypeOverride "UseLocalSettings" MinMaxOverflowLogging "UseLocalSettings" MinMaxOverflowArchiveMode "Overwrite" BlockNameDataTip off BlockParametersDataTip off BlockDescriptionStringDataTip off ToolBar on StatusBar on BrowserShowLibraryLinks off BrowserLookUnderMasks off Created "Wed May 10 09:44:20 2006" UpdateHistory "UpdateHistoryNever" ModifiedByFormat "%<Auto>" LastModifiedBy "user" ModifiedDateFormat "%<Auto>" LastModifiedDate "Wed Jun 21 22:12:23 2006" ModelVersionFormat "1.%<AutoIncrement:26>" ConfigurationManager "None" SimParamPage "Solver" LinearizationMsg "none" Profile off ParamWorkspaceSource "MATLABWorkspace" AccelSystemTargetFile "accel.tlc" AccelTemplateMakefile "accel_default_tmf" AccelMakeCommand "make_rtw" TryForcingSFcnDF off ExtModeMexFile "ext_comm" ExtModeBatchMode off ExtModeTrigType "manual" ExtModeTrigMode "normal" ExtModeTrigPort "1" ExtModeTrigElement "any" ExtModeTrigDuration 1000 ExtModeTrigHoldOff 0 ExtModeTrigDelay 0 ExtModeTrigDirection "rising" ExtModeTrigLevel 0 ExtModeArchiveMode "off" ExtModeAutoIncOneShot off ExtModeIncDirWhenArm off ExtModeAddSuffixToVar off ExtModeWriteAllDataToWs off ExtModeArmWhenConnect on ExtModeSkipDownloadWhenConnect off ExtModeLogAll on ExtModeAutoUpdateStatusClock on BufferReuse on RTWExpressionDepthLimit 5 SimulationMode "normal" Solver "ode45" SolverMode "Auto" StartTime "0.0" StopTime "100.0" MaxOrder 5 MaxStep "auto" MinStep "auto" MaxNumMinSteps "-1" InitialStep "auto" FixedStep "auto" RelTol "1e-3" AbsTol "auto" OutputOption "RefineOutputTimes" OutputTimes "[]" Refine "1" LoadExternalInput off ExternalInput "[t, u]" LoadInitialState off InitialState "xInitial" SaveTime on TimeSaveName "tout" SaveState off StateSaveName "xout" SaveOutput on OutputSaveName "yout" SaveFinalState off FinalStateName "xFinal" SaveFormat "Array" Decimation "1" LimitDataPoints on MaxDataPoints "1000" SignalLoggingName "sigsOut" ConsistencyChecking "none" ArrayBoundsChecking "none" AlgebraicLoopMsg "warning" BlockPriorityViolationMsg "warning" MinStepSizeMsg "warning" InheritedTsInSrcMsg "warning" DiscreteInheritContinuousMsg "warning" MultiTaskRateTransMsg "error" SingleTaskRateTransMsg "none" CheckForMatrixSingularity "none" IntegerOverflowMsg "warning" Int32ToFloatConvMsg "warning" ParameterDowncastMsg "error" ParameterOverflowMsg "error" ParameterPrecisionLossMsg "warning" UnderSpecifiedDataTypeMsg "none" UnnecessaryDatatypeConvMsg "none" VectorMatrixConversionMsg "none" InvalidFcnCallConnMsg "error" SignalLabelMismatchMsg "none" UnconnectedInputMsg "warning" UnconnectedOutputMsg "warning" UnconnectedLineMsg "warning" SfunCompatibilityCheckMsg "none" RTWInlineParameters off BlockReductionOpt on BooleanDataType on ConditionallyExecuteInputs on ParameterPooling on OptimizeBlockIOStorage on ZeroCross on AssertionControl "UseLocalSettings" ProdHWDeviceType "Microprocessor" ProdHWWordLengths "8,16,32,32" RTWSystemTargetFile "grt.tlc" RTWTemplateMakefile "grt_default_tmf" RTWMakeCommand "make_rtw" RTWGenerateCodeOnly off RTWRetainRTWFile off TLCProfiler off TLCDebug off TLCCoverage off TLCAssertion off BlockDefaults { Orientation "right" ForegroundColor "black" BackgroundColor "white" DropShadow off NamePlacement "normal" FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" ShowName on } BlockParameterDefaults { Block { BlockType ComplexToRealImag Output "Real and imag" } Block { BlockType DataTypeConversion DataType "auto" SaturateOnIntegerOverflow on } Block { BlockType DiscretePulseGenerator PulseType "Sample based" Amplitude "1" Period "2" PulseWidth "1" PhaseDelay "0" VectorParams1D on } Block { BlockType Display Format "short" Decimation "10" Floating off } Block { BlockType FrameConversion OutFrame "Frame-based" } Block { BlockType FromWorkspace VariableName "simulink_input" Interpolate on OutputAfterFinalValue "Extrapolation" } Block { BlockType Ground } Block { BlockType Inport Port "1" PortDimensions "-1" ShowAdditionalParam off LatchInput off DataType "auto" OutDataType "sfix(16)" OutScaling "2^0" SignalType "auto" SamplingMode "auto" Interpolate on } Block { BlockType Logic Operator "AND" Inputs "2" ShowAdditionalParam off AllPortsSameDT on OutDataTypeMode "Logical (see Advanced Sim. Parameters)" LogicDataType "uint(8)" } Block { BlockType Math Operator "exp" OutputSignalType "auto" } Block { BlockType Outport Port "1" OutputWhenDisabled "held" InitialOutput "[]" } Block { BlockType Product Inputs "2" Multiplication "Element-wise(.*)" ShowAdditionalParam off InputSameDT on OutDataTypeMode "Same as first input" OutDataType "sfix(16)" OutScaling "2^0" LockScale off RndMeth "Floor" SaturateOnIntegerOverflow on } Block { BlockType Scope Floating off ModelBased off TickLabels "OneTimeTick" ZoomMode "on" Grid "on" TimeRange "auto" YMin "-5" YMax "5" SaveToWorkspace off SaveName "ScopeData" LimitDataPoints on MaxDataPoints "5000" Decimation "1" SampleInput off } Block { BlockType "S-Function" FunctionName "system" PortCounts "[]" SFunctionModules "''" } Block { BlockType SubSystem ShowPortLabels on Permissions "ReadWrite" RTWSystemCode "Auto" RTWFcnNameOpts "Auto" RTWFileNameOpts "Auto" SimViewingDevice off DataTypeOverride "UseLocalSettings" MinMaxOverflowLogging "UseLocalSettings" } Block { BlockType Sum IconShape "rectangular" Inputs "++" ShowAdditionalParam off InputSameDT on OutDataTypeMode "Same as first input" OutDataType "sfix(16)" OutScaling "2^0" LockScale off RndMeth "Floor" SaturateOnIntegerOverflow on } Block { BlockType TriggerPort TriggerType "rising" ShowOutputPort off OutputDataType "auto" ZeroCross on } Block { BlockType ZeroOrderHold } } AnnotationDefaults { HorizontalAlignment "center" VerticalAlignment "middle" ForegroundColor "black" BackgroundColor "white" DropShadow off FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" } LineDefaults { FontName "Helvetica" FontSize 9 FontWeight "normal" FontAngle "normal" } System { Name "gyb" Location [2, 82, 1014, 721] Open on ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "A4" PaperUnits "centimeters" ZoomFactor "100" ReportName "simulink-default.rpt" Block { BlockType Reference Name "AWGN\nChannel1" Ports [1, 1] Position [835, 200, 915, 240] Orientation "down" SourceBlock "commchan2/AWGN\nChannel" SourceType "AWGN Channel" seed "1237" noiseMode "Signal to noise ratio (SNR)" EsNodB "10" SNRdB "-20" Ps "1" Tsym "1" variance "1" } Block { BlockType Reference Name "Convolutional\nEncoder" Ports [1, 1] Position [480, 95, 600, 155] SourceBlock "commcnvcod2/Convolutional\nEncoder" SourceType "Convolutional Encoder" trellis "poly2trellis(9,[753 561])" reset "None" } Block { BlockType DataTypeConversion Name "Data Type Conversion1" Position [367, 260, 423, 290] Orientation "down" } Block { BlockType DataTypeConversion Name "Data Type Conversion2" Position [365, 111, 420, 139] } Block { BlockType Display Name "Display" Ports [1] Position [680, 419, 780, 511] Decimation "1" } Block { BlockType Reference Name "Error Rate\nCalculation" Ports [2, 1] Position [540, 437, 615, 488] SourceBlock "commsink2/Error Rate\nCalculation" SourceType "Error Rate Calculation" N "102" st_delay "0" cp_mode "Entire frame" subframe "[]" PMode "Port" WsName "ErrorVec" RsMode2 off stop on numErr "500" maxBits "1e6" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [250, 25, 305, 65] SourceBlock "dspobslib/Integer Delay" SourceType "Integer Delay" delay "14" ic "0" reset_popup "None" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [280, 103, 320, 147] Operator "XOR" AllPortsSameDT off } Block { BlockType Logic Name "Logical\nOperator1" Ports [2, 1] Position [290, 214, 325, 256] Operator "XOR" AllPortsSameDT off } Block { BlockType Reference Name "M-DPSK\nDemodulator\nPassband" Ports [1, 1] Position [730, 289, 805, 341] Orientation "left" SourceBlock "commdigpbndpm2/M-DPSK\nDemodulator\nPassband" SourceType "M-DPSK Demodulator Passband" M "2" OutType "Bit" Dec "Binary" td "5e-4" numSamp "4" Fc "2e4" Ph "0" InSamp "1e-6" } Block { BlockType Reference Name "M-DPSK\nModulator\nPassband" Ports [1, 1] Position [725, 99, 800, 151] SourceBlock "commdigpbndpm2/M-DPSK\nModulator\nPassband" SourceType "M-DPSK Modulator Passband"
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