speed.exactly.c

代码优化,有效使用内存,透视优化技术,对比优化方法,如果你在追求代码效率的最大化,该资源你不能不读.

/* ---------------------------------------------------------------------------
 * @
 *		UTILITY FOR MEASURING ACTUAL MEMORY THROUGHPUT
 *					WITH ACCOUNT OF CHIPSET AND CPU LATENCY
 *		============================================================
 *
 * Build 0x001	03.04.2002
 * Build 0x002	16.05.2002
--------------------------------------------------------------------------- */

#include <DoCPU.h>

// converting float to int
#define _f2i(a) ((int) a)

// calculating the remainder of the division of larger argument by a smaller one
#define remainder(a,b) (MAX(_f2i(a),_f2i(b)) % MIN(_f2i(a),_f2i(b)))

// data input
#define _INPUT(s, var) printf(_TEXT(s));							\
	fgets(buff, MAX_STR_LEN - 1, stdin);							\
	if (buff[0]=='y' || buff[0]=='Y') var=1; else					\
	if (buff[0]=='n' || buff[0]=='N') var=0; else var=atof(buff);	\
/* end define _INPUT */

main()
{
	float Fcpu;					// CPU clock frequency
	float FSB;					// system bus frequency
	float Ftransf;				// effective system bus frequency
	float Fm;					// memory clock frequency	

	float RAS_latency;			// RAS to CAS Delay
	float CAS_latency;			// CAS Delay
	float RAS_precharge;		// RAS Precharge Delay
	float LEN_page;				// DRAM page length
	float N;					// memory width

	float BRST_LEN;				// length of the FSB packet
	float BRST_NUM;				// number of DRAM packets in one FSB packet

	float CPU_latency;			// CPU latency
	float X_CACHE;				/* relation of the processor frequency 
								^^ to L2 cache frequency */
	
	float C;					// throughput

	int fInterleaving;			// are banks interleaving?

	int fSrl;					/* 0: parallel data transfer from MCT to BIU
								^^ 1: data transfer via intermediate buffer */

	int fMCT2BIUparallel;		/* 0: sequential data transfer from buffer to BIU
								^^ 1: parallel data transfer */

	int fImmediately;			/* 0: cell is available after completing the transaction
								^^ 1: cell is available immediately */

	int Chipset_penalty = 0;	// penalty for coordinating FSB and memory frequencies
	int CPU_penalty 	= 0;	// penalty for coordinating CPU and FSB frequencies

	char buff[MAX_STR_LEN];		// buffer for strings

	// TITLE
	PRINT("=== Calculation of memory throughput with account of chipset latency ===\n");
	PRINT_TITLE; printf(_TEXT("\n-------------- enter --------------\n"));

	// data input
	_INPUT("CPU frequency     ..... (MHz)?\t", Fcpu);
	_INPUT("System bus frequency... (MHz)?\t", FSB);
	_INPUT("Data transfer rate..... (MHz)?\t", Ftransf);
	_INPUT("Memory frequency....... (MHz)?\t", Fm);
	_INPUT("RAS to CAS latency..... (CLK)?\t", RAS_latency);
	_INPUT("CAS latency............ (CLK)?\t", CAS_latency);
	_INPUT("RAS precharge.......... (CLK)?\t", RAS_precharge);
	_INPUT("DRAM page length....... (KB )?\t", LEN_page);
	_INPUT("Memory width........... (bit)?\t", N);
	_INPUT("Lenth of bus packet.... (num)?\t", BRST_LEN);
	_INPUT("Length of DRAM packet.. (num)?\t", BRST_NUM);
	_INPUT("CPU latency............ (CLK)?\t", CPU_latency);
	_INPUT("CPU/L2 CACHE............(X/x)?\t", X_CACHE);
	_INPUT("蟂equential buffer......[y,n]?\t", fSrl);
	_INPUT("Bank interleave..