📄 push_old.s
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.code 32.equ MODE_USR, 0x10.equ MODE_IRQ, 0x12.equ MODE_SVC, 0x13.equ I_BIT, 0x80.equ F_BIT, 0x40.equ IRQ_STACK, 0x0101ffff.equ PORTA_MUX, 0x09000000.equ PORTA_DIR, 0x09001604.equ PORTA_DATA, 0x09001600.equ PORT7_MUX, 0x09000020.equ PORT7_DIR, 0x09001644.equ PORT7_DATA, 0x09001640.equ GLOBAL_MASK, 0x09001200.equ TRIGGER_MODE, 0x09001204.equ TRIGGER_POLARITY, 0x09001208.equ INTERRUPT_DIRECTION, 0x0900120c.equ FIQ_STATUS, 0x09001210.equ IRQ_STATUS, 0x09001214.equ FIQ_MASK, 0x09001218.equ IRQ_MASK, 0x0900121c.equ INTERRUPT_STATUS_CLEAR, 0x09001220.equ DELAY_CNT, 0xffff.global _start_start:.text 0 b reset_handler b undefined_handler b swi_handler b prefetch_handler b abort_handler nop b irq_handler b fiq_handler .text 1reset_handler: mov r0, #MODE_IRQ | I_BIT | F_BIT msr cpsr, r0 ldr sp, =IRQ_STACK mov r0, #MODE_USR msr cpsr, r0 b startundefined_handler: movs pc, lrswi_handler: movs pc, lrprefetch_handler: subs pc, lr, #4abort_handler: subs pc, lr, #8irq_handler: stmfd sp!, {r0-r12,lr} mrs r12, cpsr orr r12, r12, #0x90 msr cpsr, r12 ldr r7, =GLOBAL_MASK ldr r1, =0x01ffff3e str r1, [r7] ldr r7, =INTERRUPT_STATUS_CLEAR ldr r1, =0x000000c1 str r1, [r7] ldr r7, =PORTA_DATA mov r1, sp str r1, [r7] ldmfd sp!, {r0-r12,lr} subs pc, lr, #4fiq_handler: subs pc, lr, #4start: ldr r0, =PORTA_MUX @setup port a ldr r1, =0x3fff str r1, [r0] ldr r0, =PORTA_DIR mov r1, #0 str r1, [r0] ldr r0, =PORT7_DIR @setup port 7 ldr r1, =0x000000ff str r1, [r0] ldr r0, =PORT7_MUX ldr r1, =0x000000a0 str r1, [r0] ldr r0, =TRIGGER_MODE @setup interrupt ldr r1, =0x00000000 str r1, [r0] ldr r0, =TRIGGER_POLARITY ldr r1, =0x00000000 str r1, [r0] ldr r0, =INTERRUPT_DIRECTION ldr r1, =0x00000000 str r1, [r0] ldr r0, =FIQ_MASK ldr r1, =0x01ffffff str r1, [r0] ldr r0, =IRQ_MASK ldr r1, =0x01ffff3e str r1, [r0] ldr r0, =GLOBAL_MASK ldr r1, =0x01ffff3e str r1, [r0] ldr r0, =INTERRUPT_STATUS_CLEAR ldr r1, =0x000000c1 str r1, [r0] /* swi 0x0 @debug swi*/ ldr r5, =PORTA_DATA mov r2, #0main_loop: str r2, [r5, #0] ldr r0, =DELAY_CNT bl delay add r2, r2, #1 b main_loopdelay: subs r0, r0, #1 bhs delay mov pc, lr.pool
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