shift.vhd

FFT基2 处理器（定点

-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic       
-- functions, and any output files any of the foregoing           
-- (including device programming or simulation files), and any    
-- associated documentation or information are expressly subject  
-- to the terms and conditions of the Altera Program License      
-- Subscription Agreement, Altera MegaCore Function License       
-- Agreement, or other applicable license agreement, including,   
-- without limitation, that your use is for the sole purpose of   
-- programming logic devices manufactured by Altera and sold by   
-- Altera or its authorized distributors.  Please refer to the    
-- applicable agreement for further details.


-- Generated by Quartus II Version 5.0 (Build Build 148 04/26/2005)
-- Created on Fri Mar 30 17:30:46 2007

LIBRARY ieee;
USE ieee.std_logic_1164.all;

--  Entity Declaration

ENTITY Shift IS
	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	PORT
	(
		Image : IN STD_LOGIC_VECTOR(34 downto 0);
		Reality : IN STD_LOGIC_VECTOR(34 downto 0);
		Image_out : OUT STD_LOGIC_VECTOR(34 downto 0);
		Reality_out : OUT STD_LOGIC_VECTOR(34 downto 0)
	);
	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	
END Shift;


--  Architecture Body

ARCHITECTURE Shift_architecture OF Shift IS

	
BEGIN

    Reality_out<="000000000000000"&Reality(34 downto 15) when Reality(34)='0' else
                 "111111111111111"&Reality(34 downto 15);
    Image_out<="000000000000000"&Image(34 downto 15) when Image(34)='0' else
               "111111111111111"&Image(34 downto 15);

END Shift_architecture;