r2processor.map.eqn

FFT基2 处理器（定点

V2L74 = CARRY(V2L74_adder_eqn);


--V2L05 is L4_Sub:inst12|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~461
V2L05_adder_eqn = ( !S1_pipeline_dffe[26] ) + ( X_i[11] ) + ( V2L74 );
V2L05 = SUM(V2L05_adder_eqn);

--V2L15 is L4_Sub:inst12|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~462
V2L15_adder_eqn = ( !S1_pipeline_dffe[26] ) + ( X_i[11] ) + ( V2L74 );
V2L15 = CARRY(V2L15_adder_eqn);


--V2L45 is L4_Sub:inst12|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~465
V2L45_adder_eqn = ( !S1_pipeline_dffe[27] ) + ( X_i[12] ) + ( V2L15 );
V2L45 = SUM(V2L45_adder_eqn);

--V2L55 is L4_Sub:inst12|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~466
V2L55_adder_eqn = ( !S1_pipeline_dffe[27] ) + ( X_i[12] ) + ( V2L15 );
V2L55 = CARRY(V2L55_adder_eqn);


--V2L85 is L4_Sub:inst12|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~469
V2L85_adder_eqn = ( !S1_pipeline_dffe[28] ) + ( X_i[13] ) + ( V2L55 );
V2L85 = SUM(V2L85_adder_eqn);

--V2L95 is L4_Sub:inst12|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~470
V2L95_adder_eqn = ( !S1_pipeline_dffe[28] ) + ( X_i[13] ) + ( V2L55 );
V2L95 = CARRY(V2L95_adder_eqn);


--V2L26 is L4_Sub:inst12|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~473
V2L26_adder_eqn = ( !S1_pipeline_dffe[29] ) + ( X_i[14] ) + ( V2L95 );
V2L26 = SUM(V2L26_adder_eqn);

--V2L36 is L4_Sub:inst12|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~474
V2L36_adder_eqn = ( !S1_pipeline_dffe[29] ) + ( X_i[14] ) + ( V2L95 );
V2L36 = CARRY(V2L36_adder_eqn);


--V2L66 is L4_Sub:inst12|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~477
V2L66_adder_eqn = ( !S1_pipeline_dffe[30] ) + ( X_i[15] ) + ( V2L36 );
V2L66 = SUM(V2L66_adder_eqn);

--V2L76 is L4_Sub:inst12|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~478
V2L76_adder_eqn = ( !S1_pipeline_dffe[30] ) + ( X_i[15] ) + ( V2L36 );
V2L76 = CARRY(V2L76_adder_eqn);


--V2L07 is L4_Sub:inst12|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~481
V2L07_adder_eqn = ( !S1_pipeline_dffe[31] ) + ( X_i[15] ) + ( V2L76 );
V2L07 = SUM(V2L07_adder_eqn);

--V2L17 is L4_Sub:inst12|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~482
V2L17_adder_eqn = ( !S1_pipeline_dffe[31] ) + ( X_i[15] ) + ( V2L76 );
V2L17 = CARRY(V2L17_adder_eqn);


--V2L47 is L4_Sub:inst12|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~485
V2L47_adder_eqn = ( !S1_pipeline_dffe[32] ) + ( X_i[15] ) + ( V2L17 );
V2L47 = SUM(V2L47_adder_eqn);

--V2L57 is L4_Sub:inst12|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~486
V2L57_adder_eqn = ( !S1_pipeline_dffe[32] ) + ( X_i[15] ) + ( V2L17 );
V2L57 = CARRY(V2L57_adder_eqn);


--V2L87 is L4_Sub:inst12|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~489
V2L87_adder_eqn = ( !S1_pipeline_dffe[34] ) + ( X_i[15] ) + ( V2L57 );
V2L87 = SUM(V2L87_adder_eqn);

--V2L97 is L4_Sub:inst12|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~490
V2L97_adder_eqn = ( !S1_pipeline_dffe[34] ) + ( X_i[15] ) + ( V2L57 );
V2L97 = CARRY(V2L97_adder_eqn);


--V2L28 is L4_Sub:inst12|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~493
V2L28_adder_eqn = ( !S1_pipeline_dffe[34] ) + ( X_i[15] ) + ( V2L97 );
V2L28 = SUM(V2L28_adder_eqn);


--V1L01 is L4_Sub:inst11|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~421
V1L01_adder_eqn = ( !T1_pipeline_dffe[16] ) + ( X_r[1] ) + ( V1L7 );
V1L01 = SUM(V1L01_adder_eqn);

--V1L11 is L4_Sub:inst11|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~422
V1L11_adder_eqn = ( !T1_pipeline_dffe[16] ) + ( X_r[1] ) + ( V1L7 );
V1L11 = CARRY(V1L11_adder_eqn);


--V1L41 is L4_Sub:inst11|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~425
V1L41_adder_eqn = ( !T1_pipeline_dffe[17] ) + ( X_r[2] ) + ( V1L11 );
V1L41 = SUM(V1L41_adder_eqn);

--V1L51 is L4_Sub:inst11|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~426
V1L51_adder_eqn = ( !T1_pipeline_dffe[17] ) + ( X_r[2] ) + ( V1L11 );
V1L51 = CARRY(V1L51_adder_eqn);


--V1L81 is L4_Sub:inst11|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~429
V1L81_adder_eqn = ( !T1_pipeline_dffe[18] ) + ( X_r[3] ) + ( V1L51 );
V1L81 = SUM(V1L81_adder_eqn);

--V1L91 is L4_Sub:inst11|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~430
V1L91_adder_eqn = ( !T1_pipeline_dffe[18] ) + ( X_r[3] ) + ( V1L51 );
V1L91 = CARRY(V1L91_adder_eqn);


--V1L22 is L4_Sub:inst11|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~433
V1L22_adder_eqn = ( !T1_pipeline_dffe[19] ) + ( X_r[4] ) + ( V1L91 );
V1L22 = SUM(V1L22_adder_eqn);

--V1L32 is L4_Sub:inst11|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~434
V1L32_adder_eqn = ( !T1_pipeline_dffe[19] ) + ( X_r[4] ) + ( V1L91 );
V1L32 = CARRY(V1L32_adder_eqn);


--V1L62 is L4_Sub:inst11|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~437
V1L62_adder_eqn = ( !T1_pipeline_dffe[20] ) + ( X_r[5] ) + ( V1L32 );
V1L62 = SUM(V1L62_adder_eqn);

--V1L72 is L4_Sub:inst11|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~438
V1L72_adder_eqn = ( !T1_pipeline_dffe[20] ) + ( X_r[5] ) + ( V1L32 );
V1L72 = CARRY(V1L72_adder_eqn);


--V1L03 is L4_Sub:inst11|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~441
V1L03_adder_eqn = ( !T1_pipeline_dffe[21] ) + ( X_r[6] ) + ( V1L72 );
V1L03 = SUM(V1L03_adder_eqn);

--V1L13 is L4_Sub:inst11|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~442
V1L13_adder_eqn = ( !T1_pipeline_dffe[21] ) + ( X_r[6] ) + ( V1L72 );
V1L13 = CARRY(V1L13_adder_eqn);


--V1L43 is L4_Sub:inst11|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~445
V1L43_adder_eqn = ( !T1_pipeline_dffe[22] ) + ( X_r[7] ) + ( V1L13 );
V1L43 = SUM(V1L43_adder_eqn);

--V1L53 is L4_Sub:inst11|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~446
V1L53_adder_eqn = ( !T1_pipeline_dffe[22] ) + ( X_r[7] ) + ( V1L13 );
V1L53 = CARRY(V1L53_adder_eqn);


--V1L83 is L4_Sub:inst11|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~449
V1L83_adder_eqn = ( !T1_pipeline_dffe[23] ) + ( X_r[8] ) + ( V1L53 );
V1L83 = SUM(V1L83_adder_eqn);

--V1L93 is L4_Sub:inst11|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~450
V1L93_adder_eqn = ( !T1_pipeline_dffe[23] ) + ( X_r[8] ) + ( V1L53 );
V1L93 = CARRY(V1L93_adder_eqn);


--V1L24 is L4_Sub:inst11|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~453
V1L24_adder_eqn = ( !T1_pipeline_dffe[24] ) + ( X_r[9] ) + ( V1L93 );
V1L24 = SUM(V1L24_adder_eqn);

--V1L34 is L4_Sub:inst11|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~454
V1L34_adder_eqn = ( !T1_pipeline_dffe[24] ) + ( X_r[9] ) + ( V1L93 );
V1L34 = CARRY(V1L34_adder_eqn);


--V1L64 is L4_Sub:inst11|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~457
V1L64_adder_eqn = ( !T1_pipeline_dffe[25] ) + ( X_r[10] ) + ( V1L34 );
V1L64 = SUM(V1L64_adder_eqn);

--V1L74 is L4_Sub:inst11|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~458
V1L74_adder_eqn = ( !T1_pipeline_dffe[25] ) + ( X_r[10] ) + ( V1L34 );
V1L74 = CARRY(V1L74_adder_eqn);


--V1L05 is L4_Sub:inst11|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~461
V1L05_adder_eqn = ( !T1_pipeline_dffe[26] ) + ( X_r[11] ) + ( V1L74 );
V1L05 = SUM(V1L05_adder_eqn);

--V1L15 is L4_Sub:inst11|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~462
V1L15_adder_eqn = ( !T1_pipeline_dffe[26] ) + ( X_r[11] ) + ( V1L74 );
V1L15 = CARRY(V1L15_adder_eqn);


--V1L45 is L4_Sub:inst11|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~465
V1L45_adder_eqn = ( !T1_pipeline_dffe[27] ) + ( X_r[12] ) + ( V1L15 );
V1L45 = SUM(V1L45_adder_eqn);

--V1L55 is L4_Sub:inst11|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~466
V1L55_adder_eqn = ( !T1_pipeline_dffe[27] ) + ( X_r[12] ) + ( V1L15 );
V1L55 = CARRY(V1L55_adder_eqn);


--V1L85 is L4_Sub:inst11|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~469
V1L85_adder_eqn = ( !T1_pipeline_dffe[28] ) + ( X_r[13] ) + ( V1L55 );
V1L85 = SUM(V1L85_adder_eqn);

--V1L95 is L4_Sub:inst11|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~470
V1L95_adder_eqn = ( !T1_pipeline_dffe[28] ) + ( X_r[13] ) + ( V1L55 );
V1L95 = CARRY(V1L95_adder_eqn);


--V1L26 is L4_Sub:inst11|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~473
V1L26_adder_eqn = ( !T1_pipeline_dffe[29] ) + ( X_r[14] ) + ( V1L95 );
V1L26 = SUM(V1L26_adder_eqn);

--V1L36 is L4_Sub:inst11|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~474
V1L36_adder_eqn = ( !T1_pipeline_dffe[29] ) + ( X_r[14] ) + ( V1L95 );
V1L36 = CARRY(V1L36_adder_eqn);


--V1L66 is L4_Sub:inst11|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~477
V1L66_adder_eqn = ( !T1_pipeline_dffe[30] ) + ( X_r[15] ) + ( V1L36 );
V1L66 = SUM(V1L66_adder_eqn);

--V1L76 is L4_Sub:inst11|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~478
V1L76_adder_eqn = ( !T1_pipeline_dffe[30] ) + ( X_r[15] ) + ( V1L36 );
V1L76 = CARRY(V1L76_adder_eqn);


--V1L07 is L4_Sub:inst11|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~481
V1L07_adder_eqn = ( !T1_pipeline_dffe[31] ) + ( X_r[15] ) + ( V1L76 );
V1L07 = SUM(V1L07_adder_eqn);

--V1L17 is L4_Sub:inst11|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~482
V1L17_adder_eqn = ( !T1_pipeline_dffe[31] ) + ( X_r[15] ) + ( V1L76 );
V1L17 = CARRY(V1L17_adder_eqn);


--V1L47 is L4_Sub:inst11|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~485
V1L47_adder_eqn = ( !T1_pipeline_dffe[32] ) + ( X_r[15] ) + ( V1L17 );
V1L47 = SUM(V1L47_adder_eqn);

--V1L57 is L4_Sub:inst11|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~486
V1L57_adder_eqn = ( !T1_pipeline_dffe[32] ) + ( X_r[15] ) + ( V1L17 );
V1L57 = CARRY(V1L57_adder_eqn);


--V1L87 is L4_Sub:inst11|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~489
V1L87_adder_eqn = ( !T1_pipeline_dffe[34] ) + ( X_r[15] ) + ( V1L57 );
V1L87 = SUM(V1L87_adder_eqn);

--V1L97 is L4_Sub:inst11|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~490
V1L97_adder_eqn = ( !T1_pipeline_dffe[34] ) + ( X_r[15] ) + ( V1L57 );
V1L97 = CARRY(V1L97_adder_eqn);


--V1L28 is L4_Sub:inst11|lpm_add_sub:lpm_add_sub_component|add_sub_doh:auto_generated|op_1~493
V1L28_adder_eqn = ( !T1_pipeline_dffe[34] ) + ( X_r[15] ) + ( V1L97 );
V1L28 = SUM(V1L28_adder_eqn);


--R2_result[0] is L2_Mul:inst5|lpm_mult:lpm_mult_component|mult_nqq:auto_generated|result[0]
--DSP Block Operation Mode: Simple Multiplier (18-bit)
R2_result[0] = R2_mac_mult2;

--R2_result[1] is L2_Mul:inst5|lpm_mult:lpm_mult_component|mult_nqq:auto_generated|result[1]
R2_result[1] = R2L2;

--R2_result[2] is L2_Mul:inst5|lpm_mult:lpm_mult_component|mult_nqq:auto_generated|result[2]
R2_result[2] = R2L3;

--R2_result[3] is L2_Mul:inst5|lpm_mult:lpm_mult_component|mult_nqq:auto_generated|result[3]
R2_result[3] = R2L4;

--R2_result[4] is L2_Mul:inst5|lpm_mult:lpm_mult_component|mult_nqq:auto_generated|result[4]
R2_result[4] = R2L5;

--R2_result[5] is L2_Mul:inst5|lpm_mult:lpm_mult_component|mult_nqq:auto_generated|result[5]
R2_result[5] = R2L6;

--R2_result[6] is L2_Mul:inst5|lpm_mult:lpm_mult_component|mult_nqq:auto_generated|result[6]
R2_result[6] = R2L7;

--R2_result[7] is L2_Mul:inst5|lpm_mult:lpm_mult_component|mult_nqq:auto_generated|result[7]
R2_result[7] = R2L8;

--R2_result[8] is L2_Mul:inst5|lpm_mult:lpm_mult_component|mult_nqq:auto_generated|result[8]
R2_result[8] = R2L9;

--R2_result[9] is L2_Mul:inst5|lpm_mult:lpm_mult_component|mult_nqq:auto_generated|result[9]
R2_result[9] = R2L01;

--R2_result[10] is L2_Mul:inst5|lpm_mult:lpm_mult_component|mult_nqq:auto_generated|result[10]
R2_result[10] = R2L11;

--R2_result[11] is L2_Mul:inst5|lpm_mult:lpm_mult_component|mult_nqq:auto_generated|result[11]
R2_result[11] = R2L21;

--R2_result[12] is L2_Mul:inst5|lpm_mult:lpm_mult_component|mult_nqq:auto_generated|result[12]
R2_result[12] = R2L31;

--R2_result[13] is L2_Mul:inst5|lpm_mult:lpm_mult_component|mult_nqq:auto_generated|result[13]
R2_result[13] = R2L41;

--R2_result[14] is L2_Mul:inst5|lpm_mult:lpm_mult_component|mult_nqq:auto_generated|result[14]
R2_result[14] = R2L51;

--R2_result[15] is L2_Mul:inst5|lpm_mult:lpm_mult_component|mult_nqq:auto_generated|result[15]
R2_result[15] = R2L61;

--R2_result[16] is L2_Mul:inst5|lpm_mult:lpm_mult_component|mult_nqq:auto_generated|result[16