out_transform.vhd

FFT基2 处理器（定点

-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic       
-- functions, and any output files any of the foregoing           
-- (including device programming or simulation files), and any    
-- associated documentation or information are expressly subject  
-- to the terms and conditions of the Altera Program License      
-- Subscription Agreement, Altera MegaCore Function License       
-- Agreement, or other applicable license agreement, including,   
-- without limitation, that your use is for the sole purpose of   
-- programming logic devices manufactured by Altera and sold by   
-- Altera or its authorized distributors.  Please refer to the    
-- applicable agreement for further details.


-- Generated by Quartus II Version 5.0 (Build Build 148 04/26/2005)
-- Created on Thu Mar 29 20:21:28 2007

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

--  Entity Declaration

ENTITY Out_Transform IS
	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	PORT
	(
		C_r : IN STD_LOGIC_VECTOR(34 downto 0);
		C_i : IN STD_LOGIC_VECTOR(34 downto 0);
		D_r : IN STD_LOGIC_VECTOR(34 downto 0);
		D_i : IN STD_LOGIC_VECTOR(34 downto 0);
		D_r_out : OUT STD_LOGIC_VECTOR(15 downto 0);
		C_i_out : OUT STD_LOGIC_VECTOR(15 downto 0);
		C_r_out : OUT STD_LOGIC_VECTOR(15 downto 0);
		D_i_out : OUT STD_LOGIC_VECTOR(15 downto 0)
	);
	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	
END Out_Transform;


--  Architecture Body

ARCHITECTURE Out_Transform_architecture OF Out_Transform IS
    	
BEGIN

    C_r_out<=C_r(19)&C_r(14 downto 0) when C_r(19 downto 15)="11111" 
                                        or C_r(19 downto 15)="00000" else 
                               
             "0111111111111111" when C_r(19)='0' else
                  --set it max for the 16bits for the signal's overflow 
  
             "1000000000000000";
                  --set it min for the 16bits

    C_i_out<=C_i(19)&C_i(14 downto 0) when C_i(19 downto 15)="11111" 
                                        or C_i(19 downto 15)="00000" else 
             "0111111111111111" when C_i(19)='0' else   
             "1000000000000000";

    D_r_out<=D_r(19)&D_r(14 downto 0) when D_r(19 downto 15)="11111" 
                                        or D_r(19 downto 15)="00000" else 
             "0111111111111111" when D_r(19)='0' else   
             "1000000000000000"; 

    D_i_out<=D_i(19)&D_i(14 downto 0) when D_i(19 downto 15)="11111" 
                                        or D_i(19 downto 15)="00000" else 
             "0111111111111111" when D_i(19)='0' else   
             "1000000000000000"; 

END Out_Transform_architecture;