l4_sub.cmp

FFT基2 处理器（定点

--Copyright (C) 1991-2005 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions 
--and other software and tools, and its AMPP partner logic       
--functions, and any output files any of the foregoing           
--(including device programming or simulation files), and any    
--associated documentation or information are expressly subject  
--to the terms and conditions of the Altera Program License      
--Subscription Agreement, Altera MegaCore Function License       
--Agreement, or other applicable license agreement, including,   
--without limitation, that your use is for the sole purpose of   
--programming logic devices manufactured by Altera and sold by   
--Altera or its authorized distributors.  Please refer to the    
--applicable agreement for further details.


component L4_Sub
	PORT
	(
		dataa		: IN STD_LOGIC_VECTOR (34 DOWNTO 0);
		datab		: IN STD_LOGIC_VECTOR (34 DOWNTO 0);
		clock		: IN STD_LOGIC ;
		aclr		: IN STD_LOGIC ;
		clken		: IN STD_LOGIC ;
		result		: OUT STD_LOGIC_VECTOR (34 DOWNTO 0)
	);
end component;