in_transform.vhd

FFT基2 处理器（定点

-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic       
-- functions, and any output files any of the foregoing           
-- (including device programming or simulation files), and any    
-- associated documentation or information are expressly subject  
-- to the terms and conditions of the Altera Program License      
-- Subscription Agreement, Altera MegaCore Function License       
-- Agreement, or other applicable license agreement, including,   
-- without limitation, that your use is for the sole purpose of   
-- programming logic devices manufactured by Altera and sold by   
-- Altera or its authorized distributors.  Please refer to the    
-- applicable agreement for further details.


-- Generated by Quartus II Version 5.0 (Build Build 148 04/26/2005)
-- Created on Thu Mar 29 14:50:21 2007

LIBRARY ieee;
USE ieee.std_logic_1164.all;


--  Entity Declaration

ENTITY In_Transform IS
	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	PORT
	(
		X_r : IN STD_LOGIC_VECTOR(15 downto 0);
		X_i : IN STD_LOGIC_VECTOR(15 downto 0);
		Y_r : IN STD_LOGIC_VECTOR(15 downto 0);
		Y_i : IN STD_LOGIC_VECTOR(15 downto 0);
		W_r : IN STD_LOGIC_VECTOR(15 downto 0);
		W_i : IN STD_LOGIC_VECTOR(15 downto 0);
		X_r_out : OUT STD_LOGIC_VECTOR(34 downto 0);
		X_i_out : OUT STD_LOGIC_VECTOR(34 downto 0);
		Y_r_out : OUT STD_LOGIC_VECTOR(16 downto 0);
		Y_i_out : OUT STD_LOGIC_VECTOR(16 downto 0);
		W_r_out : OUT STD_LOGIC_VECTOR(16 downto 0);
		W_i_out : OUT STD_LOGIC_VECTOR(16 downto 0)
	);
	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	
END In_Transform;


--  Architecture Body

ARCHITECTURE In_Transform_architecture OF In_Transform IS

	
BEGIN

    with X_i(15) select
        X_i_out<=X_i(15)&"0000000000000000000"&X_i(14 downto 0) when '0',   --extense the signal to 35 bits to avoid overflow
                 X_i(15)&"1111111111111111111"&X_i(14 downto 0) when '1',
                 null when others;

    with X_r(15) select
        X_r_out<=X_r(15)&"0000000000000000000"&X_r(14 downto 0) when '0',
                 X_r(15)&"1111111111111111111"&X_r(14 downto 0) when '1',
                 null when others;

    Y_r_out<=Y_r(15)&Y_r(15)&Y_r(14 downto 0);  --add one more sign bit to avoid overflow
    Y_i_out<=Y_i(15)&Y_i(15)&Y_i(14 downto 0);
    W_r_out<=W_r(15)&W_r(15)&W_r(14 downto 0);
    W_i_out<=W_i(15)&W_i(15)&W_i(14 downto 0);

END In_Transform_architecture;