lottery number generator.txt

Lottery Number Generator的vhdl程序

Structural Model of Lottery Number Generator
--top level design for lottery number generator
--version 2 uses 6 number registers
library ieee;
use ieee.std_logic_1164.all;
entity lottery2 is
port(clock, reset, next_no : in std_logic;
numled : out std_logic_vector(1 to 6);
seg0, seg1 : out std_logic_vector(6 downto 0));
end entity lottery2;
architecture structure of lottery2 is
component lottreg
port(clock, clear, load : in std_logic;
d : in std_logic_vector(7 downto 0);
q : out std_logic_vector(7 downto 0));
end component;
component count49
h t t p : / / w w w . a m i . b o l t o n . a c . u k / c o u r s e w a r e / a d v e d a / v h d l / v h d l e x m p . h t m l ( 3 4 o f 6 7 ) [ 2 3 / 1 / 2 0 0 2 4 : 1 5 : 0 9 ]
Examples of VHDL Descriptions
port(clock, clear : in std_logic;
cnt1to49 : buffer std_logic_vector(7 downto 0));
end component;
component seg7dec --see file bcd2seg.vhd
PORT(bcdin : IN std_logic_vector(3 DOWNTO 0);
segout : OUT std_logic_vector(6 DOWNTO 0));
end component;
component lottcont2
port(clock, reset, next_no, match : in std_logic;
loadnum1, loadnum2, loadnum3, loadnum4,
loadnum5, loadnum6, sample : out std_logic;
seldisplay : out natural range 0 to 5;
numled : out std_logic_vector(1 to 6));
end component;
signal match : std_logic;
signal sample : std_logic;
signal seldisplay : natural range 0 to 5;
signal count, samp_reg, display : std_logic_vector(7 downto 0);
signal num_reg1, num_reg2, num_reg3 : std_logic_vector(7 downto 0);
signal num_reg4, num_reg5, num_reg6 : std_logic_vector(7 downto 0);
signal loadnum1, loadnum2, loadnum3, loadnum4, loadnum5, loadnum6 :
std_logic;
begin
counter : count49
port map (clock => clock, clear => reset, cnt1to49 => count);
sample_reg : lottreg
port map (clock => clock, clear => reset,
load => sample, d => count, q => samp_reg);
--number registers
numreg1 : lottreg port map
(clock => clock, clear => reset, load => loadnum1,
d => samp_reg, q => num_reg1);
numreg2 : lottreg port map
(clock => clock, clear => reset, load => loadnum2,
d => samp_reg, q => num_reg2);
numreg3 : lottreg port map
(clock => clock, clear => reset, load => loadnum3,
d => samp_reg, q => num_reg3);
numreg4 : lottreg port map
(clock => clock, clear => reset, load => loadnum4,
d => samp_reg, q => num_reg4);
numreg5 : lottreg port map
(clock => clock, clear => reset, load => loadnum5,
d => samp_reg, q => num_reg5);
numreg6 : lottreg port map
(clock => clock, clear => reset, load => loadnum6,
d => samp_reg, q => num_reg6);
compare : match <= '1' when ((((samp_reg = num_reg1)
or (samp_reg = num_reg2))
or (samp_reg = num_reg3))
or (samp_reg = num_reg4))
or (samp_reg = num_reg5)
else '0';
display_mux : with seldisplay select
display <= num_reg1 when 0,
num_reg2 when 1,
num_reg3 when 2,
h t t p : / / w w w . a m i . b o l t o n . a c . u k / c o u r s e w a r e / a d v e d a / v h d l / v h d l e x m p . h t m l ( 3 5 o f 6 7 ) [ 2 3 / 1 / 2 0 0 2 4 : 1 5 : 0 9 ]
Examples of VHDL Descriptions
num_reg4 when 3,
num_reg5 when 4,
num_reg6 when 5,
"00000000" when others;
segdec0 : seg7dec
port map (bcdin => display(3 downto 0), segout => seg0);
segdec1 : seg7dec
port map (bcdin => display(7 downto 4), segout => seg1);
controller : lottcont2
port map (clock => clock, reset => reset, next_no => next_no,
match => match, loadnum1 => loadnum1,
loadnum2 => loadnum2, loadnum3 => loadnum3,
loadnum4 => loadnum4, loadnum5 => loadnum5,
loadnum6 => loadnum6, sample => sample,
seldisplay => seldisplay,
numled => numled);
end architecture structure;