📄 notch_60.lst
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/*****************************************************************************
* timer 0 interrupt service routine
***************************************************************************/
void timer0_isr(void)
{
028A 3064 MOVLW 64h TMR0=100; /* reload value for 1ms period */
028B 1283 BCF STATUS,RP0
028C 0081 MOVWF TMR0
028D 3001 MOVLW 01h PORTB.0=!PORTB.0; /* toggle PORTB.0 */
028E 0686 XORWF PORTB
028F 14A5 BSF 25,1 sample_flag=active; /* set sample flag */
0290 0008 RETURN }
void main()
{
/* initialize OPTION register */
0291 3003 MOVLW 03h OPTION=0b00000011; /* assign prescaler to T0 */
0292 1683 BSF STATUS,RP0
0293 0081 MOVWF TMR0
/* initialize INTCON register (keep GIE inactive!) */
0294 018B CLRF INTCON INTCON=0b00000000; /* disable all interrupts */
/* initialize PIE1 and PIE2 registers (periphreal interrupts) */
0295 018C CLRF PIR1 PIE1=0b00000000; /* disable all peripheral interrupts */
0296 018D CLRF PIR2 PIE2=0b00000000;
/* initialize T1CON and T2CON registers */
0297 1283 BCF STATUS,RP0 T1CON=0b00000000; /* T1 not used */
0298 0190 CLRF T1CON
0299 0192 CLRF T2CON T2CON=0b00000000; /* T2 not used */
/* initialize CCPxCON registers */
029A 300C MOVLW 0Ch CCP1CON=0b00001100; /* set CCP1CON for PWM mode */
029B 0097 MOVWF CCP1CON
MPC "C" COMPILER BC.193 22-Aug-1995 PAGE 19
029C 019D CLRF CCP2CON CCP2CON=0b00000000; /* CCP2CON=0 (PWM 2 not used) */
/* initialize SSPCON register */
029D 0194 CLRF SSPCON SSPCON=0b00000000; /* serial port - not used */
/* initialize ADCONx registers */
029E 019F CLRF ADCON0 ADCON0=0b00000000; /* a-d converter */
029F 3002 MOVLW 02h ADCON1=0b00000010;
02A0 1683 BSF STATUS,RP0
02A1 009F MOVWF ADCON0
/* initialize TRISx register (port pins as inputs or outputs) */
02A2 300F MOVLW 0Fh TRISA=0b00001111;
02A3 0085 MOVWF PORTA
02A4 0186 CLRF PORTB TRISB=0b00000000;
02A5 30FB MOVLW FBh TRISC=0b11111011;
02A6 0087 MOVWF PORTC
02A7 30FF MOVLW FFh TRISD=0b11111111;
02A8 0088 MOVWF PORTD
02A9 0089 MOVWF PORTE TRISE=0b11111111;
/* clear watchdog timer (not used) */
02AA 0064 CLRWDT CLRWDT();
/* initialize program bit variables */
02AB 1283 BCF STATUS,RP0 FLAGS=0b00000000;
02AC 01A5 CLRF 25
/* intialize output port pins */
02AD 0186 CLRF PORTB PORTB=0;
/* enable interrupts... */
02AE 168B BSF INTCON,T0IE INTCON.T0IE=1; /* peripheral interrupt enable */
02AF 178B BSF INTCON,GIE INTCON.GIE=1; /* global interrupt enable */
02B0 3040 MOVLW 40h init_PWM(0x40); /* init PWM port */
02B1 2025 CALL 0025h
02B2 2195 CALL 0195h init_filter(); /* init filter */
while(1){
02B3 1283 BCF STATUS,RP0
02B4 1CA5 BTFSS 25,1
02B5 2AB3 GOTO 02B3h
02B6 while(!sample_flag){} /* wait for sample clock flag to be set */
02B6 1283 BCF STATUS,RP0 sample_flag=0; /* clear sample clock flag */
02B7 10A5 BCF 25,1
02B8 3001 MOVLW 01h x_n=get_sample(1); /* read ADC channel 1 into x(n) */
02B9 2005 CALL 0005h
02BA 1283 BCF STATUS,RP0
02BB 00B5 MOVWF 35
if(FILTER==1){ /* if filter enabled */
02BC 21F7 CALL 01F7h filter(); /* call filter routine */
}
02BD 2AC1 GOTO 02C1h else{ /* or else write x(n) to y(n) (talkthru) */
02BE 0835 MOVF 35,W y_n=x_n;
MPC "C" COMPILER BC.193 22-Aug-1995 PAGE 20
02BF 00B6 MOVWF 36
02C0 01B7 CLRF 37
}
02C1 1283 BCF STATUS,RP0 write_PWM((char)y_n,0); /* write y_n to PWM port 1 */
02C2 0836 MOVF 36,W
02C3 0084 MOVWF FSR
02C4 3000 MOVLW 00h
02C5 203D CALL 003Dh
02C6 2AB3 GOTO 02B3h }
02C7 0008 RETURN }
#pragma option +l;
/*
MPC14 Library V1.11
These routines may be adapted for any purpose when
used with the MPC Code Development system. No
warranty is implied or given as to their usability
for any purpose.
Parts of these routines are adapted with permission from
software supplied by Microchip the remainder is a
translation of the standard software routines developed
by Byte Craft Limited for embedded system compiler support.
*/
/***********************************************************************
Multiply Divide and Modulus routines for the MPC
Code Development System. These routines are used by
the compiler as the part of the MPC14.LIB library.
(c) Copyright 1988,1991,1994,1995
Byte Craft Limited
Waterloo, Ontario
Canada N2J 4E4
(519) 888-6911
Walter Banks
************************************************************************/
//-----------------------------------------------------------------------
void __MUL16x16(void)
{
bits R0 @ &_t;
bits R1 @ &_u;
R0 = *(&__longAC) * *(&__longIX);
R1 = FSR;
R1 += (*(&__longAC+1) * (*(&__longIX )));
R1 += (*(&__longAC ) * (*(&__longIX+1)));
FSR = R1; // instead of __FSRImage in 12-bit
WREG = R0; // instead of __WImage in 12-bit
} // __MUL16x16()
MPC "C" COMPILER BC.193 22-Aug-1995 PAGE 21
//-----------------------------------------------------------------------
void __MUL8x8(void)
{
bits R @ _r;
bits Q @ _q;
bits S @ _s;
Q = WREG;
WREG = FSR;
FSR = 0;
S = 0;
R = 0;
R.3 = 1;
do {
STATUS.C = 0 ; // Clear carry bit in the status Reg.
if (Q.0 == 1) FSR += WREG; // High Byte
RRF(FSR);
RRF(S );
RRF(Q );
} while (--R);
WREG = S;
} // __MUL8X8(void)
//-----------------------------------------------------------------------
void __DIV8BY8(void)
{
char ACCaLO @ FSR;
char ACCbLO @ _q;
char ACCcLO @ _r;
char ACCdLO @ _s;
char temp @ _t;
ACCdLO = WREG;
temp = 8; // for 8 shifts
ACCbLO = 0;
ACCcLO = 0;
do {
STATUS.C=0;
RLF(ACCdLO);
RLF(ACCcLO);
if (ACCaLO <= ACCcLO) {
ACCcLO -= ACCaLO; // c-a into c
STATUS.C = 1; // shift a 1 into b (result)
}
RLF(ACCbLO);
} while (--temp); // loop until all bits checked
FSR=ACCbLO;
WREG=ACCcLO;
} // __DIV8X8
//-----------------------------------------------------------------------
void __LDIV(void)
{
unsigned long ACCa @ &__longIX;
char ACCaLO @ &__longIX;
MPC "C" COMPILER BC.193 22-Aug-1995 PAGE 22
char ACCaHI @ &__longIX+1;
unsigned long ACCb @ &__longAC;
char ACCbLO @ &ACCb;
char ACCbHI @ &ACCb+1;
unsigned long ACCc @ &long_q;
char ACCcLO @ &ACCc;
char ACCcHI @ &ACCc+1;
unsigned long ACCd @ &long_s;
char ACCdLO @ &ACCd;
char ACCdHI @ &ACCd+1;
char temp @ _u;
temp = 0x10; // for 16 shifts
ACCdHI = *(&__longAC+1); // move ACCb to ACCd
ACCdLO = *(&__longAC); //
ACCbHI = 0;
ACCbLO = 0;
ACCcHI = 0;
ACCcLO = 0;
do {
STATUS.C = 0;
RLF(ACCdLO);
RLF(ACCdHI);
RLF(ACCcLO);
RLF(ACCcHI);
if (ACCc >= ACCa) {
ACCc = ACCc - ACCa; // c-a into c
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