booth_com.tan.qmsg

布思基四乘法器实现,很好用,快来看,希望对大家有所帮助.

{ "Info" "ITDB_FULL_TCO_RESULT" "CLK PRO\[4\] pro_reg\[4\] 5.095 ns register " "Info: tco from clock \"CLK\" to destination pin \"PRO\[4\]\" through register \"pro_reg\[4\]\" is 5.095 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.093 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.093 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns CLK 1 CLK PIN_14 15 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_14; Fanout = 15; CLK Node = 'CLK'" {  } { { "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com_cmp.qrpt" "" { Report "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com_cmp.qrpt" Compiler "booth_com" "UNKNOWN" "V1" "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com.quartus_db" { Floorplan "D:/Practice/Booth_mutipler/pr/booth_com/" "" "" { CLK } "NODE_NAME" } "" } } { "../../src/booth_com.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_com.v" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.792 ns) + CELL(0.574 ns) 2.093 ns pro_reg\[4\] 2 REG LC_X4_Y3_N2 1 " "Info: 2: + IC(0.792 ns) + CELL(0.574 ns) = 2.093 ns; Loc. = LC_X4_Y3_N2; Fanout = 1; REG Node = 'pro_reg\[4\]'" {  } { { "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com_cmp.qrpt" "" { Report "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com_cmp.qrpt" Compiler "booth_com" "UNKNOWN" "V1" "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com.quartus_db" { Floorplan "D:/Practice/Booth_mutipler/pr/booth_com/" "" "1.366 ns" { CLK pro_reg[4] } "NODE_NAME" } "" } } { "../../src/booth_com.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_com.v" 42 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.301 ns 62.16 % " "Info: Total cell delay = 1.301 ns ( 62.16 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.792 ns 37.84 % " "Info: Total interconnect delay = 0.792 ns ( 37.84 % )" {  } {  } 0}  } { { "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com_cmp.qrpt" "" { Report "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com_cmp.qrpt" Compiler "booth_com" "UNKNOWN" "V1" "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com.quartus_db" { Floorplan "D:/Practice/Booth_mutipler/pr/booth_com/" "" "2.093 ns" { CLK pro_reg[4] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.093 ns" { CLK CLK~combout pro_reg[4] } { 0.000ns 0.000ns 0.792ns } { 0.000ns 0.727ns 0.574ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.235 ns + " "Info: + Micro clock to output delay of source is 0.235 ns" {  } { { "../../src/booth_com.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_com.v" 42 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.767 ns + Longest register pin " "Info: + Longest register to pin delay is 2.767 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pro_reg\[4\] 1 REG LC_X4_Y3_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y3_N2; Fanout = 1; REG Node = 'pro_reg\[4\]'" {  } { { "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com_cmp.qrpt" "" { Report "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com_cmp.qrpt" Compiler "booth_com" "UNKNOWN" "V1" "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com.quartus_db" { Floorplan "D:/Practice/Booth_mutipler/pr/booth_com/" "" "" { pro_reg[4] } "NODE_NAME" } "" } } { "../../src/booth_com.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_com.v" 42 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.313 ns) + CELL(1.454 ns) 2.767 ns PRO\[4\] 2 PIN PIN_66 0 " "Info: 2: + IC(1.313 ns) + CELL(1.454 ns) = 2.767 ns; Loc. = PIN_66; Fanout = 0; PIN Node = 'PRO\[4\]'" {  } { { "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com_cmp.qrpt" "" { Report "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com_cmp.qrpt" Compiler "booth_com" "UNKNOWN" "V1" "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com.quartus_db" { Floorplan "D:/Practice/Booth_mutipler/pr/booth_com/" "" "2.767 ns" { pro_reg[4] PRO[4] } "NODE_NAME" } "" } } { "../../src/booth_com.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_com.v" 29 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.454 ns 52.55 % " "Info: Total cell delay = 1.454 ns ( 52.55 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.313 ns 47.45 % " "Info: Total interconnect delay = 1.313 ns ( 47.45 % )" {  } {  } 0}  } { { "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com_cmp.qrpt" "" { Report "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com_cmp.qrpt" Compiler "booth_com" "UNKNOWN" "V1" "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com.quartus_db" { Floorplan "D:/Practice/Booth_mutipler/pr/booth_com/" "" "2.767 ns" { pro_reg[4] PRO[4] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.767 ns" { pro_reg[4] PRO[4] } { 0.000ns 1.313ns } { 0.000ns 1.454ns } } }  } 0}  } { { "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com_cmp.qrpt" "" { Report "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com_cmp.qrpt" Compiler "booth_com" "UNKNOWN" "V1" "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com.quartus_db" { Floorplan "D:/Practice/Booth_mutipler/pr/booth_com/" "" "2.093 ns" { CLK pro_reg[4] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.093 ns" { CLK CLK~combout pro_reg[4] } { 0.000ns 0.000ns 0.792ns } { 0.000ns 0.727ns 0.574ns } } } { "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com_cmp.qrpt" "" { Report "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com_cmp.qrpt" Compiler "booth_com" "UNKNOWN" "V1" "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com.quartus_db" { Floorplan "D:/Practice/Booth_mutipler/pr/booth_com/" "" "2.767 ns" { pro_reg[4] PRO[4] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.767 ns" { pro_reg[4] PRO[4] } { 0.000ns 1.313ns } { 0.000ns 1.454ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "m2_reg\[1\] M2\[1\] CLK -0.636 ns register " "Info: th for register \"m2_reg\[1\]\" (data pin = \"M2\[1\]\", clock pin = \"CLK\") is -0.636 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.093 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 2.093 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns CLK 1 CLK PIN_14 15 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_14; Fanout = 15; CLK Node = 'CLK'" {  } { { "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com_cmp.qrpt" "" { Report "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com_cmp.qrpt" Compiler "booth_com" "UNKNOWN" "V1" "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com.quartus_db" { Floorplan "D:/Practice/Booth_mutipler/pr/booth_com/" "" "" { CLK } "NODE_NAME" } "" } } { "../../src/booth_com.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_com.v" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.792 ns) + CELL(0.574 ns) 2.093 ns m2_reg\[1\] 2 REG LC_X4_Y2_N4 16 " "Info: 2: + IC(0.792 ns) + CELL(0.574 ns) = 2.093 ns; Loc. = LC_X4_Y2_N4; Fanout = 16; REG Node = 'm2_reg\[1\]'" {  } { { "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com_cmp.qrpt" "" { Report "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com_cmp.qrpt" Compiler "booth_com" "UNKNOWN" "V1" "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com.quartus_db" { Floorplan "D:/Practice/Booth_mutipler/pr/booth_com/" "" "1.366 ns" { CLK m2_reg[1] } "NODE_NAME" } "" } } { "../../src/booth_com.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_com.v" 37 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.301 ns 62.16 % " "Info: Total cell delay = 1.301 ns ( 62.16 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.792 ns 37.84 % " "Info: Total interconnect delay = 0.792 ns ( 37.84 % )" {  } {  } 0}  } { { "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com_cmp.qrpt" "" { Report "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com_cmp.qrpt" Compiler "booth_com" "UNKNOWN" "V1" "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com.quartus_db" { Floorplan "D:/Practice/Booth_mutipler/pr/booth_com/" "" "2.093 ns" { CLK m2_reg[1] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.093 ns" { CLK CLK~combout m2_reg[1] } { 0.000ns 0.000ns 0.792ns } { 0.000ns 0.727ns 0.574ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.138 ns + " "Info: + Micro hold delay of destination is 0.138 ns" {  } { { "../../src/booth_com.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_com.v" 37 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.867 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.867 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.708 ns) 0.708 ns M2\[1\] 1 PIN PIN_58 1 " "Info: 1: + IC(0.000 ns) + CELL(0.708 ns) = 0.708 ns; Loc. = PIN_58; Fanout = 1; PIN Node = 'M2\[1\]'" {  } { { "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com_cmp.qrpt" "" { Report "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com_cmp.qrpt" Compiler "booth_com" "UNKNOWN" "V1" "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com.quartus_db" { Floorplan "D:/Practice/Booth_mutipler/pr/booth_com/" "" "" { M2[1] } "NODE_NAME" } "" } } { "../../src/booth_com.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_com.v" 33 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.984 ns) + CELL(0.175 ns) 2.867 ns m2_reg\[1\] 2 REG LC_X4_Y2_N4 16 " "Info: 2: + IC(1.984 ns) + CELL(0.175 ns) = 2.867 ns; Loc. = LC_X4_Y2_N4; Fanout = 16; REG Node = 'm2_reg\[1\]'" {  } { { "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com_cmp.qrpt" "" { Report "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com_cmp.qrpt" Compiler "booth_com" "UNKNOWN" "V1" "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com.quartus_db" { Floorplan "D:/Practice/Booth_mutipler/pr/booth_com/" "" "2.159 ns" { M2[1] m2_reg[1] } "NODE_NAME" } "" } } { "../../src/booth_com.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_com.v" 37 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.883 ns 30.80 % " "Info: Total cell delay = 0.883 ns ( 30.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.984 ns 69.20 % " "Info: Total interconnect delay = 1.984 ns ( 69.20 % )" {  } {  } 0}  } { { "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com_cmp.qrpt" "" { Report "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com_cmp.qrpt" Compiler "booth_com" "UNKNOWN" "V1" "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com.quartus_db" { Floorplan "D:/Practice/Booth_mutipler/pr/booth_com/" "" "2.867 ns" { M2[1] m2_reg[1] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.867 ns" { M2[1] M2[1]~combout m2_reg[1] } { 0.000ns 0.000ns 1.984ns } { 0.000ns 0.708ns 0.175ns } } }  } 0}  } { { "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com_cmp.qrpt" "" { Report "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com_cmp.qrpt" Compiler "booth_com" "UNKNOWN" "V1" "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com.quartus_db" { Floorplan "D:/Practice/Booth_mutipler/pr/booth_com/" "" "2.093 ns" { CLK m2_reg[1] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.093 ns" { CLK CLK~combout m2_reg[1] } { 0.000ns 0.000ns 0.792ns } { 0.000ns 0.727ns 0.574ns } } } { "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com_cmp.qrpt" "" { Report "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com_cmp.qrpt" Compiler "booth_com" "UNKNOWN" "V1" "D:/Practice/Booth_mutipler/pr/booth_com/db/booth_com.quartus_db" { Floorplan "D:/Practice/Booth_mutipler/pr/booth_com/" "" "2.867 ns" { M2[1] m2_reg[1] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.867 ns" { M2[1] M2[1]~combout m2_reg[1] } { 0.000ns 0.000ns 1.984ns } { 0.000ns 0.708ns 0.175ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 05 21:38:07 2006 " "Info: Processing ended: Tue Sep 05 21:38:07 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}