booth_com.vo

布思基四乘法器实现,很好用,快来看,希望对大家有所帮助.

// Copyright (C) 1991-2005 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic       
// functions, and any output files any of the foregoing           
// (including device programming or simulation files), and any    
// associated documentation or information are expressly subject  
// to the terms and conditions of the Altera Program License      
// Subscription Agreement, Altera MegaCore Function License       
// Agreement, or other applicable license agreement, including,   
// without limitation, that your use is for the sole purpose of   
// programming logic devices manufactured by Altera and sold by   
// Altera or its authorized distributors.  Please refer to the    
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version"

// DATE "09/05/2006 21:38:11"

// 
// Device: Altera EPM240T100C3 Package TQFP100
// 

// 
// This Verilog file should be used for ModelSim (Verilog) only
// 

`timescale 1 ps/ 1 ps

module 	booth_com (
	CLK,
	RST_,
	M2,
	M1,
	PRO);
input 	CLK;
input 	RST_;
input 	[3:0] M2;
input 	[3:0] M1;
output 	[7:0] PRO;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri0 devoe;
// synopsys translate_off
initial $sdf_annotate("booth_com_v.sdo");
// synopsys translate_on

wire \pro_reg[3]~540 ;
wire \CLK~combout ;
wire \M1[0]~combout ;
wire \RST_~combout ;
wire \m1_reg[0] ;
wire \M2[1]~combout ;
wire \pro_tmp~131 ;
wire \M1[1]~combout ;
wire \pro_tmp~130 ;
wire \add~712 ;
wire \add~712COUT1_804 ;
wire \add~735 ;
wire \add~717 ;
wire \add~717COUT1_809 ;
wire \add~730 ;
wire \Select~1264 ;
wire \m1_reg[1] ;
wire \M2[3]~combout ;
wire \M2[0]~combout ;
wire \m2_reg[1]~49 ;
wire \pro_tmp~132 ;
wire \add~737 ;
wire \add~737COUT1_805 ;
wire \add~756 ;
wire \add~732 ;
wire \add~732COUT1_810 ;
wire \add~751 ;
wire \Select~1267 ;
wire \Select~1268 ;
wire \M1[2]~combout ;
wire \Select~1265 ;
wire \add~727 ;
wire \add~727COUT1_819 ;
wire \add~741 ;
wire \add~722 ;
wire \add~722COUT1_814 ;
wire \add~746 ;
wire \Select~1266 ;
wire \m1_reg[2] ;
wire \M2[2]~combout ;
wire \M1[3]~combout ;
wire \m1_reg[3] ;
wire \m2_reg[2] ;
wire \m2_reg[1] ;
wire \m2_reg[0] ;
wire \pro_reg[0] ;
wire \always3~0 ;
wire \add~715 ;
wire \add~710 ;
wire \pro_reg~534 ;
wire \pro_reg[1] ;
wire \m1_tmp[2]~47 ;
wire \add~720 ;
wire \add~725 ;
wire \pro_reg~536 ;
wire \pro_reg[2] ;
wire \add~740 ;
wire \Select~1273 ;
wire \pro_tmp~133 ;
wire \pro_reg[3]~540COUT0_550 ;
wire \pro_reg[3]~540COUT1_551 ;
wire \pro_reg[3] ;
wire \m2_reg[3] ;
wire \add~753 ;
wire \add~753COUT1_812 ;
wire \add~772 ;
wire \add~758 ;
wire \add~758COUT1_807 ;
wire \add~777 ;
wire \Select~1270 ;
wire \Select~1271 ;
wire \add~743 ;
wire \add~743COUT1_820 ;
wire \add~762 ;
wire \add~748 ;
wire \add~748COUT1_815 ;
wire \add~767 ;
wire \Select~1269 ;
wire \Select~1274 ;
wire \add~761 ;
wire \pro_reg[3]~518 ;
wire \pro_reg[3]~518COUT1_552 ;
wire \pro_reg[4] ;
wire \add~769 ;
wire \add~769COUT1_817 ;
wire \add~788 ;
wire \add~764 ;
wire \add~764COUT1_822 ;
wire \add~783 ;
wire \Select~1272 ;
wire \Select~1275 ;
wire \add~782 ;
wire \pro_reg[4]~522 ;
wire \pro_reg[4]~522COUT1_554 ;
wire \pro_reg[5] ;
wire \add~793 ;
wire \pro_reg[5]~526 ;
wire \pro_reg[5]~526COUT1_556 ;
wire \pro_reg[7] ;


// atom is at PIN_14
maxii_io \CLK~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\CLK~combout ),
	.padio(CLK));
// synopsys translate_off
defparam \CLK~I .operation_mode = "input";
// synopsys translate_on

// atom is at PIN_36
maxii_io \M1[0]~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\M1[0]~combout ),
	.padio(M1[0]));
// synopsys translate_off
defparam \M1[0]~I .operation_mode = "input";
// synopsys translate_on

// atom is at PIN_12
maxii_io \RST_~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\RST_~combout ),
	.padio(RST_));
// synopsys translate_off
defparam \RST_~I .operation_mode = "input";
// synopsys translate_on

// atom is at LC_X4_Y2_N5
maxii_lcell \m1_reg[0]~I (
// Equation(s):
// \pro_tmp~130  = m1_reg[0] & (\m2_reg[1]  $ \m2_reg[0] )
// \m1_reg[0]  = DFFEAS(\pro_tmp~130 , GLOBAL(\CLK~combout ), GLOBAL(\RST_~combout ), , , \M1[0]~combout , , , VCC)

	.clk(\CLK~combout ),
	.dataa(\m2_reg[1] ),
	.datab(vcc),
	.datac(\M1[0]~combout ),
	.datad(\m2_reg[0] ),
	.aclr(!\RST_~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\pro_tmp~130 ),
	.regout(\m1_reg[0] ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \m1_reg[0]~I .operation_mode = "normal";
defparam \m1_reg[0]~I .synch_mode = "on";
defparam \m1_reg[0]~I .register_cascade_mode = "off";
defparam \m1_reg[0]~I .sum_lutc_input = "qfbk";
defparam \m1_reg[0]~I .lut_mask = "50A0";
defparam \m1_reg[0]~I .output_mode = "reg_and_comb";
// synopsys translate_on

// atom is at PIN_58
maxii_io \M2[1]~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\M2[1]~combout ),
	.padio(M2[1]));
// synopsys translate_off
defparam \M2[1]~I .operation_mode = "input";
// synopsys translate_on

// atom is at LC_X4_Y2_N4
maxii_lcell \m2_reg[1]~I (
// Equation(s):
// \pro_tmp~131  = \m1_reg[0]  & (\m2_reg[2]  $ (m2_reg[1] # \m2_reg[0] ))
// \m2_reg[1]  = DFFEAS(\pro_tmp~131 , GLOBAL(\CLK~combout ), GLOBAL(\RST_~combout ), , , \M2[1]~combout , , , VCC)

	.clk(\CLK~combout ),
	.dataa(\m1_reg[0] ),
	.datab(\m2_reg[2] ),
	.datac(\M2[1]~combout ),
	.datad(\m2_reg[0] ),
	.aclr(!\RST_~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\pro_tmp~131 ),
	.regout(\m2_reg[1] ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \m2_reg[1]~I .operation_mode = "normal";
defparam \m2_reg[1]~I .synch_mode = "on";
defparam \m2_reg[1]~I .register_cascade_mode = "off";
defparam \m2_reg[1]~I .sum_lutc_input = "qfbk";
defparam \m2_reg[1]~I .lut_mask = "2228";
defparam \m2_reg[1]~I .output_mode = "reg_and_comb";
// synopsys translate_on

// atom is at PIN_69
maxii_io \M1[1]~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\M1[1]~combout ),
	.padio(M1[1]));
// synopsys translate_off
defparam \M1[1]~I .operation_mode = "input";
// synopsys translate_on

// atom is at LC_X4_Y2_N6
maxii_lcell \add~710_I (
// Equation(s):
// \add~710  = \pro_tmp~130  $ \m2_reg[0] 
// \add~712  = CARRY(\pro_tmp~130  # !\m2_reg[0] )
// \add~712COUT1_804  = CARRY(\pro_tmp~130  # !\m2_reg[0] )

	.clk(gnd),
	.dataa(\pro_tmp~130 ),
	.datab(\m2_reg[0] ),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\add~710 ),
	.regout(),
	.cout(),
	.cout0(\add~712 ),
	.cout1(\add~712COUT1_804 ));
// synopsys translate_off
defparam \add~710_I .operation_mode = "arithmetic";
defparam \add~710_I .synch_mode = "off";
defparam \add~710_I .register_cascade_mode = "off";
defparam \add~710_I .sum_lutc_input = "datac";
defparam \add~710_I .lut_mask = "66BB";
defparam \add~710_I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC_X4_Y2_N7
maxii_lcell \add~735_I (
// Equation(s):
// \add~735  = \m2_reg[1]  $ \pro_tmp~131  $ !\add~712 
// \add~737  = CARRY(\m2_reg[1]  & (!\add~712  # !\pro_tmp~131 ) # !\m2_reg[1]  & !\pro_tmp~131  & !\add~712 )
// \add~737COUT1_805  = CARRY(\m2_reg[1]  & (!\add~712COUT1_804  # !\pro_tmp~131 ) # !\m2_reg[1]  & !\pro_tmp~131  & !\add~712COUT1_804 )

	.clk(gnd),
	.dataa(\m2_reg[1] ),
	.datab(\pro_tmp~131 ),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(\add~712 ),
	.cin1(\add~712COUT1_804 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\add~735 ),
	.regout(),
	.cout(),
	.cout0(\add~737 ),
	.cout1(\add~737COUT1_805 ));
// synopsys translate_off
defparam \add~735_I .operation_mode = "arithmetic";
defparam \add~735_I .synch_mode = "off";
defparam \add~735_I .register_cascade_mode = "off";
defparam \add~735_I .sum_lutc_input = "cin";
defparam \add~735_I .lut_mask = "692B";
defparam \add~735_I .cin0_used = "true";
defparam \add~735_I .cin1_used = "true";
defparam \add~735_I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC_X5_Y2_N1
maxii_lcell \add~715_I (
// Equation(s):
// \add~715  = \pro_tmp~130  $ \m2_reg[0] 
// \add~717  = CARRY(\pro_tmp~130  & \m2_reg[0] )
// \add~717COUT1_809  = CARRY(\pro_tmp~130  & \m2_reg[0] )

	.clk(gnd),
	.dataa(\pro_tmp~130 ),
	.datab(\m2_reg[0] ),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\add~715 ),
	.regout(),
	.cout(),
	.cout0(\add~717 ),
	.cout1(\add~717COUT1_809 ));
// synopsys translate_off
defparam \add~715_I .operation_mode = "arithmetic";
defparam \add~715_I .synch_mode = "off";
defparam \add~715_I .register_cascade_mode = "off";
defparam \add~715_I .sum_lutc_input = "datac";
defparam \add~715_I .lut_mask = "6688";
defparam \add~715_I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC_X5_Y2_N2
maxii_lcell \add~730_I (
// Equation(s):
// \add~730  = \m2_reg[1]  $ \pro_tmp~131  $ \add~717 
// \add~732  = CARRY(\m2_reg[1]  & !\pro_tmp~131  & !\add~717  # !\m2_reg[1]  & (!\add~717  # !\pro_tmp~131 ))
// \add~732COUT1_810  = CARRY(\m2_reg[1]  & !\pro_tmp~131  & !\add~717COUT1_809  # !\m2_reg[1]  & (!\add~717COUT1_809  # !\pro_tmp~131 ))

	.clk(gnd),
	.dataa(\m2_reg[1] ),
	.datab(\pro_tmp~131 ),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(\add~717 ),
	.cin1(\add~717COUT1_809 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\add~730 ),
	.regout(),
	.cout(),
	.cout0(\add~732 ),
	.cout1(\add~732COUT1_810 ));
// synopsys translate_off
defparam \add~730_I .operation_mode = "arithmetic";
defparam \add~730_I .synch_mode = "off";
defparam \add~730_I .register_cascade_mode = "off";
defparam \add~730_I .sum_lutc_input = "cin";
defparam \add~730_I .lut_mask = "9617";
defparam \add~730_I .cin0_used = "true";
defparam \add~730_I .cin1_used = "true";
defparam \add~730_I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC_X5_Y2_N0
maxii_lcell \Select~1264_I (
// Equation(s):
// \Select~1264  = \m1_reg[0]  & (\add~730 ) # !\m1_reg[0]  & \add~735 

	.clk(gnd),
	.dataa(vcc),
	.datab(\add~735 ),
	.datac(\m1_reg[0] ),
	.datad(\add~730 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Select~1264 ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Select~1264_I .operation_mode = "normal";
defparam \Select~1264_I .synch_mode = "off";
defparam \Select~1264_I .register_cascade_mode = "off";
defparam \Select~1264_I .sum_lutc_input = "datac";
defparam \Select~1264_I .lut_mask = "FC0C";
defparam \Select~1264_I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC_X5_Y3_N5
maxii_lcell \m1_reg[1]~I (
// Equation(s):
// \Select~1265  = \pro_tmp~131  & (\Select~1264  # \m1_reg[0]  $ !m1_reg[1]) # !\pro_tmp~131  & \Select~1264  & (\m1_reg[0]  $ m1_reg[1])
// \m1_reg[1]  = DFFEAS(\Select~1265 , GLOBAL(\CLK~combout ), GLOBAL(\RST_~combout ), , , \M1[1]~combout , , , VCC)

	.clk(\CLK~combout ),
	.dataa(\pro_tmp~131 ),
	.datab(\m1_reg[0] ),
	.datac(\M1[1]~combout ),
	.datad(\Select~1264 ),
	.aclr(!\RST_~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Select~1265 ),
	.regout(\m1_reg[1] ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \m1_reg[1]~I .operation_mode = "normal";
defparam \m1_reg[1]~I .synch_mode = "on";
defparam \m1_reg[1]~I .register_cascade_mode = "off";
defparam \m1_reg[1]~I .sum_lutc_input = "qfbk";
defparam \m1_reg[1]~I .lut_mask = "BE82";
defparam \m1_reg[1]~I .output_mode = "reg_and_comb";
// synopsys translate_on

// atom is at PIN_15
maxii_io \M2[3]~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\M2[3]~combout ),
	.padio(M2[3]));
// synopsys translate_off
defparam \M2[3]~I .operation_mode = "input";
// synopsys translate_on

// atom is at PIN_17
maxii_io \M2[0]~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\M2[0]~combout ),
	.padio(M2[0]));
// synopsys translate_off
defparam \M2[0]~I .operation_mode = "input";
// synopsys translate_on

// atom is at LC_X4_Y2_N0
maxii_lcell \m2_reg[0]~I (
// Equation(s):
// \m2_reg[1]~49  = !\m2_reg[1]  & (!m2_reg[0] & !\m2_reg[2] )
// \m2_reg[0]  = DFFEAS(\m2_reg[1]~49 , GLOBAL(\CLK~combout ), GLOBAL(\RST_~combout ), , , \M2[0]~combout , , , VCC)

	.clk(\CLK~combout ),
	.dataa(\m2_reg[1] ),
	.datab(vcc),
	.datac(\M2[0]~combout ),
	.datad(\m2_reg[2] ),
	.aclr(!\RST_~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),