booth_pipeline.tan.qmsg

布思基四乘法器实现,很好用,快来看,希望对大家有所帮助.

{ "Info" "ITDB_FULL_TCO_RESULT" "CLK PRO\[7\] pro_reg\[7\] 4.688 ns register " "Info: tco from clock \"CLK\" to destination pin \"PRO\[7\]\" through register \"pro_reg\[7\]\" is 4.688 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.093 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.093 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns CLK 1 CLK PIN_14 61 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_14; Fanout = 61; CLK Node = 'CLK'" {  } { { "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline_cmp.qrpt" "" { Report "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline_cmp.qrpt" Compiler "booth_pipeline" "UNKNOWN" "V1" "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline.quartus_db" { Floorplan "D:/Practice/Booth_mutipler/pr/booth_pipeline/" "" "" { CLK } "NODE_NAME" } "" } } { "../../src/booth_pipeline.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_pipeline.v" 30 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.792 ns) + CELL(0.574 ns) 2.093 ns pro_reg\[7\] 2 REG LC_X2_Y2_N9 2 " "Info: 2: + IC(0.792 ns) + CELL(0.574 ns) = 2.093 ns; Loc. = LC_X2_Y2_N9; Fanout = 2; REG Node = 'pro_reg\[7\]'" {  } { { "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline_cmp.qrpt" "" { Report "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline_cmp.qrpt" Compiler "booth_pipeline" "UNKNOWN" "V1" "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline.quartus_db" { Floorplan "D:/Practice/Booth_mutipler/pr/booth_pipeline/" "" "1.366 ns" { CLK pro_reg[7] } "NODE_NAME" } "" } } { "../../src/booth_pipeline.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_pipeline.v" 61 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.301 ns 62.16 % " "Info: Total cell delay = 1.301 ns ( 62.16 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.792 ns 37.84 % " "Info: Total interconnect delay = 0.792 ns ( 37.84 % )" {  } {  } 0}  } { { "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline_cmp.qrpt" "" { Report "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline_cmp.qrpt" Compiler "booth_pipeline" "UNKNOWN" "V1" "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline.quartus_db" { Floorplan "D:/Practice/Booth_mutipler/pr/booth_pipeline/" "" "2.093 ns" { CLK pro_reg[7] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.093 ns" { CLK CLK~combout pro_reg[7] } { 0.000ns 0.000ns 0.792ns } { 0.000ns 0.727ns 0.574ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.235 ns + " "Info: + Micro clock to output delay of source is 0.235 ns" {  } { { "../../src/booth_pipeline.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_pipeline.v" 61 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.360 ns + Longest register pin " "Info: + Longest register to pin delay is 2.360 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pro_reg\[7\] 1 REG LC_X2_Y2_N9 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y2_N9; Fanout = 2; REG Node = 'pro_reg\[7\]'" {  } { { "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline_cmp.qrpt" "" { Report "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline_cmp.qrpt" Compiler "booth_pipeline" "UNKNOWN" "V1" "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline.quartus_db" { Floorplan "D:/Practice/Booth_mutipler/pr/booth_pipeline/" "" "" { pro_reg[7] } "NODE_NAME" } "" } } { "../../src/booth_pipeline.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_pipeline.v" 61 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.906 ns) + CELL(1.454 ns) 2.360 ns PRO\[7\] 2 PIN PIN_15 0 " "Info: 2: + IC(0.906 ns) + CELL(1.454 ns) = 2.360 ns; Loc. = PIN_15; Fanout = 0; PIN Node = 'PRO\[7\]'" {  } { { "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline_cmp.qrpt" "" { Report "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline_cmp.qrpt" Compiler "booth_pipeline" "UNKNOWN" "V1" "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline.quartus_db" { Floorplan "D:/Practice/Booth_mutipler/pr/booth_pipeline/" "" "2.360 ns" { pro_reg[7] PRO[7] } "NODE_NAME" } "" } } { "../../src/booth_pipeline.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_pipeline.v" 28 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.454 ns 61.61 % " "Info: Total cell delay = 1.454 ns ( 61.61 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.906 ns 38.39 % " "Info: Total interconnect delay = 0.906 ns ( 38.39 % )" {  } {  } 0}  } { { "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline_cmp.qrpt" "" { Report "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline_cmp.qrpt" Compiler "booth_pipeline" "UNKNOWN" "V1" "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline.quartus_db" { Floorplan "D:/Practice/Booth_mutipler/pr/booth_pipeline/" "" "2.360 ns" { pro_reg[7] PRO[7] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.360 ns" { pro_reg[7] PRO[7] } { 0.000ns 0.906ns } { 0.000ns 1.454ns } } }  } 0}  } { { "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline_cmp.qrpt" "" { Report "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline_cmp.qrpt" Compiler "booth_pipeline" "UNKNOWN" "V1" "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline.quartus_db" { Floorplan "D:/Practice/Booth_mutipler/pr/booth_pipeline/" "" "2.093 ns" { CLK pro_reg[7] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.093 ns" { CLK CLK~combout pro_reg[7] } { 0.000ns 0.000ns 0.792ns } { 0.000ns 0.727ns 0.574ns } } } { "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline_cmp.qrpt" "" { Report "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline_cmp.qrpt" Compiler "booth_pipeline" "UNKNOWN" "V1" "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline.quartus_db" { Floorplan "D:/Practice/Booth_mutipler/pr/booth_pipeline/" "" "2.360 ns" { pro_reg[7] PRO[7] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.360 ns" { pro_reg[7] PRO[7] } { 0.000ns 0.906ns } { 0.000ns 1.454ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "m1_reg\[2\] M1\[2\] CLK -0.599 ns register " "Info: th for register \"m1_reg\[2\]\" (data pin = \"M1\[2\]\", clock pin = \"CLK\") is -0.599 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.093 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 2.093 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns CLK 1 CLK PIN_14 61 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_14; Fanout = 61; CLK Node = 'CLK'" {  } { { "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline_cmp.qrpt" "" { Report "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline_cmp.qrpt" Compiler "booth_pipeline" "UNKNOWN" "V1" "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline.quartus_db" { Floorplan "D:/Practice/Booth_mutipler/pr/booth_pipeline/" "" "" { CLK } "NODE_NAME" } "" } } { "../../src/booth_pipeline.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_pipeline.v" 30 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.792 ns) + CELL(0.574 ns) 2.093 ns m1_reg\[2\] 2 REG LC_X7_Y1_N1 3 " "Info: 2: + IC(0.792 ns) + CELL(0.574 ns) = 2.093 ns; Loc. = LC_X7_Y1_N1; Fanout = 3; REG Node = 'm1_reg\[2\]'" {  } { { "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline_cmp.qrpt" "" { Report "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline_cmp.qrpt" Compiler "booth_pipeline" "UNKNOWN" "V1" "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline.quartus_db" { Floorplan "D:/Practice/Booth_mutipler/pr/booth_pipeline/" "" "1.366 ns" { CLK m1_reg[2] } "NODE_NAME" } "" } } { "../../src/booth_pipeline.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_pipeline.v" 35 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.301 ns 62.16 % " "Info: Total cell delay = 1.301 ns ( 62.16 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.792 ns 37.84 % " "Info: Total interconnect delay = 0.792 ns ( 37.84 % )" {  } {  } 0}  } { { "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline_cmp.qrpt" "" { Report "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline_cmp.qrpt" Compiler "booth_pipeline" "UNKNOWN" "V1" "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline.quartus_db" { Floorplan "D:/Practice/Booth_mutipler/pr/booth_pipeline/" "" "2.093 ns" { CLK m1_reg[2] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.093 ns" { CLK CLK~combout m1_reg[2] } { 0.000ns 0.000ns 0.792ns } { 0.000ns 0.727ns 0.574ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.138 ns + " "Info: + Micro hold delay of destination is 0.138 ns" {  } { { "../../src/booth_pipeline.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_pipeline.v" 35 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.830 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.830 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.708 ns) 0.708 ns M1\[2\] 1 PIN PIN_52 1 " "Info: 1: + IC(0.000 ns) + CELL(0.708 ns) = 0.708 ns; Loc. = PIN_52; Fanout = 1; PIN Node = 'M1\[2\]'" {  } { { "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline_cmp.qrpt" "" { Report "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline_cmp.qrpt" Compiler "booth_pipeline" "UNKNOWN" "V1" "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline.quartus_db" { Floorplan "D:/Practice/Booth_mutipler/pr/booth_pipeline/" "" "" { M1[2] } "NODE_NAME" } "" } } { "../../src/booth_pipeline.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_pipeline.v" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.383 ns) + CELL(0.739 ns) 2.830 ns m1_reg\[2\] 2 REG LC_X7_Y1_N1 3 " "Info: 2: + IC(1.383 ns) + CELL(0.739 ns) = 2.830 ns; Loc. = LC_X7_Y1_N1; Fanout = 3; REG Node = 'm1_reg\[2\]'" {  } { { "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline_cmp.qrpt" "" { Report "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline_cmp.qrpt" Compiler "booth_pipeline" "UNKNOWN" "V1" "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline.quartus_db" { Floorplan "D:/Practice/Booth_mutipler/pr/booth_pipeline/" "" "2.122 ns" { M1[2] m1_reg[2] } "NODE_NAME" } "" } } { "../../src/booth_pipeline.v" "" { Text "D:/Practice/Booth_mutipler/src/booth_pipeline.v" 35 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.447 ns 51.13 % " "Info: Total cell delay = 1.447 ns ( 51.13 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.383 ns 48.87 % " "Info: Total interconnect delay = 1.383 ns ( 48.87 % )" {  } {  } 0}  } { { "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline_cmp.qrpt" "" { Report "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline_cmp.qrpt" Compiler "booth_pipeline" "UNKNOWN" "V1" "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline.quartus_db" { Floorplan "D:/Practice/Booth_mutipler/pr/booth_pipeline/" "" "2.830 ns" { M1[2] m1_reg[2] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.830 ns" { M1[2] M1[2]~combout m1_reg[2] } { 0.000ns 0.000ns 1.383ns } { 0.000ns 0.708ns 0.739ns } } }  } 0}  } { { "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline_cmp.qrpt" "" { Report "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline_cmp.qrpt" Compiler "booth_pipeline" "UNKNOWN" "V1" "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline.quartus_db" { Floorplan "D:/Practice/Booth_mutipler/pr/booth_pipeline/" "" "2.093 ns" { CLK m1_reg[2] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.093 ns" { CLK CLK~combout m1_reg[2] } { 0.000ns 0.000ns 0.792ns } { 0.000ns 0.727ns 0.574ns } } } { "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline_cmp.qrpt" "" { Report "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline_cmp.qrpt" Compiler "booth_pipeline" "UNKNOWN" "V1" "D:/Practice/Booth_mutipler/pr/booth_pipeline/db/booth_pipeline.quartus_db" { Floorplan "D:/Practice/Booth_mutipler/pr/booth_pipeline/" "" "2.830 ns" { M1[2] m1_reg[2] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.830 ns" { M1[2] M1[2]~combout m1_reg[2] } { 0.000ns 0.000ns 1.383ns } { 0.000ns 0.708ns 0.739ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 05 22:02:58 2006 " "Info: Processing ended: Tue Sep 05 22:02:58 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}