at91_x55.rdf

基本的几个引用程序,来看卡发的有用程序,别错过了.

RTC_IER.bits.5.enum.1.name=Error: This register should always read zeros

##                       RTC_IDR

RTC_IDR.name=RTC_IDR
RTC_IDR.width=32
RTC_IDR.access=memorymapped
RTC_IDR.address=RTC_BASE+0x0024
RTC_IDR.type=bitfield
RTC_IDR.byteEndian=little
RTC_IDR.bits.0.name=Reserved 
RTC_IDR.bits.0.range=5..31
RTC_IDR.bits.1.name=CALEV
RTC_IDR.bits.1.range=4..4
RTC_IDR.bits.1.type=enum
RTC_IDR.bits.1.enum.0.name=Disable Calandar Event Interrupt *** Write Only ***
RTC_IDR.bits.1.enum.1.name=Error: This register should always read zeros 
RTC_IDR.bits.2.name=TIMEV
RTC_IDR.bits.2.range=3..3
RTC_IDR.bits.2.type=enum
RTC_IDR.bits.2.enum.0.name=Disable Time Event Interrupt *** Write Only ***
RTC_IDR.bits.2.enum.1.name=Error: This register should always read zeros 
RTC_IDR.bits.3.name=SEC
RTC_IDR.bits.3.range=2..2
RTC_IDR.bits.3.type=enum
RTC_IDR.bits.3.enum.0.name=Disable Second Event Interrupt *** Write Only ***
RTC_IDR.bits.3.enum.1.name=Error: This register should always read zeros 
RTC_IDR.bits.4.name=ALARM
RTC_IDR.bits.4.range=1..1
RTC_IDR.bits.4.type=enum
RTC_IDR.bits.4.enum.0.name=Disable Alarm Interrupt *** Write Only ***
RTC_IDR.bits.4.enum.1.name=Error: This register should always read zeros 
RTC_IDR.bits.5.name=ACKUPD
RTC_IDR.bits.5.range=0..0
RTC_IDR.bits.5.type=enum
RTC_IDR.bits.5.enum.0.name=Disable Acknowledge Update Interrupt *** Write Only ***
RTC_IDR.bits.5.enum.1.name=Error: This register should always read zeros 

##                       RTC_IMR

RTC_IMR.name=RTC_IMR
RTC_IMR.width=32
RTC_IMR.access=memorymapped
RTC_IMR.address=RTC_BASE+0x0028
RTC_IMR.type=bitfield
RTC_IMR.byteEndian=little
RTC_IMR.permission.write=none
RTC_IMR.bits.0.name=Reserved
RTC_IMR.bits.0.range=5..31
RTC_IMR.bits.1.name=CALEV
RTC_IMR.bits.1.range=4..4
RTC_IMR.bits.1.type=enum
RTC_IMR.bits.1.enum.0.name=Calendar Event Interrupt Disabled
RTC_IMR.bits.1.enum.1.name=Calendar Event Interrupt Enabled
RTC_IMR.bits.2.name=TIMEV
RTC_IMR.bits.2.range=3..3
RTC_IMR.bits.2.type=enum
RTC_IMR.bits.2.enum.0.name=Time Event Interrupt Disabled
RTC_IMR.bits.2.enum.1.name= Event Interrupt Enabled
RTC_IMR.bits.3.name=SEC
RTC_IMR.bits.3.range=2..2
RTC_IMR.bits.3.type=enum
RTC_IMR.bits.3.enum.0.name=Second Event Interrupt Disabled
RTC_IMR.bits.3.enum.1.name=Second Event Interrupt Enabled
RTC_IMR.bits.4.name=ALARM
RTC_IMR.bits.4.range=1..1
RTC_IMR.bits.4.type=enum
RTC_IMR.bits.4.enum.0.name=Alarm Interrupt Disabled
RTC_IMR.bits.4.enum.1.name=Alarm Interrupt Enabled
RTC_IMR.bits.5.name=ACKUPD
RTC_IMR.bits.5.range=0..0
RTC_IMR.bits.5.type=enum
RTC_IMR.bits.5.enum.0.name=Acknowledge Update Interrupt Disabled
RTC_IMR.bits.5.enum.1.name=Acknowledge Update Interrupt Enabled

##                       RTC_VER

RTC_VER.name=RTC_VER
RTC_VER.width=32
RTC_VER.access=memorymapped
RTC_VER.address=RTC_BASE+0x002C
RTC_VER.type=bitfield
RTC_VER.byteEndian=little
RTC_VER.permission.write=none
RTC_VER.bits.0.name=Reserved
RTC_VER.bits.0.range=4..31
RTC_VER.bits.1.name=NVCAL
RTC_VER.bits.1.range=3..3
RTC_VER.bits.1.type=enum
RTC_VER.bits.1.enum.0.name=No Invalid data detected
RTC_VER.bits.1.enum.1.name=Invalid data detected
RTC_VER.bits.2.name=NVTAL
RTC_VER.bits.2.range=2..2
RTC_VER.bits.2.type=enum
RTC_VER.bits.2.enum.0.name=No Invalid data detected
RTC_VER.bits.2.enum.1.name=Invalid data detected
RTC_VER.bits.3.name=NVC
RTC_VER.bits.3.range=1..1
RTC_VER.bits.3.type=enum
RTC_VER.bits.3.enum.0.name=No Invalid data detected
RTC_VER.bits.3.enum.1.name=Invalid data detected
RTC_VER.bits.4.name=NVT
RTC_VER.bits.4.range=0..0
RTC_VER.bits.4.type=enum
RTC_VER.bits.4.enum.0.name=No Invalid data detected
RTC_VER.bits.4.enum.1.name=Invalid data detected


############################## WD ##############################

~define.WD_BASE=0xFFFF8000

group.WD.name=WD: Watchdog

group.WD.register.0=WD_OMR
group.WD.register.3=WD_CMR
group.WD.register.4=WD_CR
group.WD.register.5=WD_SR

##				WD_OMR

##WD_OMR
WD_OMR.width=32
WD_OMR.access=memorymapped
WD_OMR.address=WD_BASE+0x00
WD_OMR.byteEndian=little
WD_OMR.type=bitfield

WD_OMR.bits.0.name=WDEN
WD_OMR.bits.0.range=0..0
WD_OMR.bits.0.type=enum
WD_OMR.bits.0.enum.0.name=Watch dog Disabled
WD_OMR.bits.0.enum.1.name=Watch dog Enable

WD_OMR.bits.1.name=RSTEN
WD_OMR.bits.1.range=1..1
WD_OMR.bits.1.type=enum
WD_OMR.bits.1.enum.0.name=WD Reset Disabled
WD_OMR.bits.1.enum.1.name=WD Reset Enabled

WD_OMR.bits.2.name=IRQEN
WD_OMR.bits.2.range=2..2
WD_OMR.bits.2.type=enum
WD_OMR.bits.2.enum.0.name=WD Interrupt Disabled
WD_OMR.bits.2.enum.1.name=WD Interrupt  Enabled

WD_OMR.bits.3.name=EXTEN
WD_OMR.bits.3.range=3..3
WD_OMR.bits.3.type=enum
WD_OMR.bits.3.enum.0.name=WD Extern signal Disabled
WD_OMR.bits.3.enum.1.name=WD Extern signal Enabled

WD_OMR.bits.4.name=OKEY
WD_OMR.bits.4.range=4..15
WD_OMR.bits.4.type=enum
WD_OMR.bits.4.enum.0.name=Overflow Access Key is 0x234 *** Write Only ***

WD_OMR.bits.5.name=Reserved
WD_OMR.bits.5.range=16..31

##				WD_CMR

WD_CMR.width=32
WD_CMR.access=memorymapped
WD_CMR.address=WD_BASE+0x04
WD_CMR.byteEndian=little
WD_CMR.type=bitfield

WD_CMR.bits.0.name=WDCLKS 
WD_CMR.bits.0.range=0..1 
WD_CMR.bits.0.type=enum 
WD_CMR.bits.0.enum.0.name=MCKI/32 Clock Selected 
WD_CMR.bits.0.enum.1.name=MCKI/128 Clock Selected 
WD_CMR.bits.0.enum.0.name=MCKI/1024 Clock Selected 
WD_CMR.bits.0.enum.1.name=MCKI/4096 Clock Selected 

WD_CMR.bits.1.name=HPCV
WD_CMR.bits.1.range=2..5

WD_CMR.bits.2.name=Reserved
WD_CMR.bits.2.range=6..6

WD_CMR.bits.3.name=CKEY
WD_CMR.bits.3.range=7..15
WD_CMR.bits.3.type=enum
WD_CMR.bits.3.enum.0.name=Clock Access Key is 0x06E *** Write Only ***

WD_CMR.bits.4.name=Reserved
WD_CMR.bits.4.range=16..31

##				WD_CR
WD_CR.width=32
WD_CR.access=memorymapped
WD_CR.address=WD_BASE+0x08
WD_CR.byteEndian=little
WD_CR.type=bitfield
WD_CR.bits.0.name=RSTKEY
WD_CR.bits.0.range=0..15
WD_CR.bits.0.type=enum
WD_CR.bits.0.enum.0.name=Restart Key is 0xC071 *** Write Only ***
WD_CR.bits.1.name=Reserved
WD_CR.bits.1.range=16..31

##				WD_SR
WD_SR.width=32
WD_SR.access=memorymapped
WD_SR.permission.write=none
WD_SR.address=WD_BASE+0x0C
WD_SR.byteEndian=little
WD_SR.type=bitfield
WD_SR.bits.0.name=WDOVF
WD_SR.bits.0.range=0..0
WD_SR.bits.0.type=enum
WD_SR.bits.0.enum.0.name=No Watchdog Overflow occurred
WD_SR.bits.0.enum.1.name=Watchdog Overflow occurred
WD_SR.bits.1.name=Reserved
WD_SR.bits.1.range=1..31


############################## AIC  ##############################

~define.AIC_BASE=0xFFFFF000

group.AIC.name=AIC: Advanced Interrupt Controller

group.AIC.register.0=AIC_SMR0_FIQ
group.AIC.register.2=AIC_SMR1_SWIRQ
group.AIC.register.4=AIC_SMR2_US0IRQ
group.AIC.register.6=AIC_SMR3_US1IRQ
group.AIC.register.8=AIC_SMR4_US3IRQ
group.AIC.register.10=AIC_SMR5_SPIRQ
group.AIC.register.12=AIC_SMR6_TC0IRQ
group.AIC.register.14=AIC_SMR7_TC1IRQ
group.AIC.register.16=AIC_SMR8_TC2IRQ
group.AIC.register.18=AIC_SMR9_TC3IRQ
group.AIC.register.20=AIC_SMR10_TC4IRQ
group.AIC.register.22=AIC_SMR11_TC5IRQ
group.AIC.register.24=AIC_SMR12_WDIRQ
group.AIC.register.26=AIC_SMR13_PIOAIRQ
group.AIC.register.28=AIC_SMR14_PIOBIRQ
group.AIC.register.30=AIC_SMR15_ADC0IRQ
group.AIC.register.32=AIC_SMR16_ADC1IRQ
group.AIC.register.34=AIC_SMR17_DCA0IRQ
group.AIC.register.36=AIC_SMR18_DCA1IRQ
group.AIC.register.38=AIC_SMR19_RTCIRQ
group.AIC.register.40=AIC_SMR20_APMCIRQ


group.AIC.register.46=AIC_SMR23_IRQ6
group.AIC.register.48=AIC_SMR24_IRQ5
group.AIC.register.50=AIC_SMR25_IRQ4
group.AIC.register.52=AIC_SMR26_IRQ3
group.AIC.register.54=AIC_SMR27_IRQ2
group.AIC.register.56=AIC_SMR28_IRQ1
group.AIC.register.58=AIC_SMR29_IRQ0
group.AIC.register.60=AIC_SMR30_COMMTX
group.AIC.register.62=AIC_SMR31_COMMRX

group.AIC.register.100=AIC_SVR0_FIQ
group.AIC.register.102=AIC_SVR1_SWIRQ
group.AIC.register.104=AIC_SVR2_US0IRQ
group.AIC.register.106=AIC_SVR3_US1IRQ
group.AIC.register.108=AIC_SVR4_US3IRQ
group.AIC.register.110=AIC_SVR5_SPIRQ
group.AIC.register.112=AIC_SVR6_TC0IRQ
group.AIC.register.114=AIC_SVR7_TC1IRQ
group.AIC.register.116=AIC_SVR8_TC2IRQ
group.AIC.register.118=AIC_SVR9_TC3IRQ
group.AIC.register.120=AIC_SVR10_TC4IRQ
group.AIC.register.122=AIC_SVR11_TC5IRQ
group.AIC.register.124=AIC_SVR12_WDIRQ
group.AIC.register.126=AIC_SVR13_PIOAIRQ
group.AIC.register.128=AIC_SVR14_PIOBIRQ
group.AIC.register.130=AIC_SVR15_ADC0IRQ
group.AIC.register.132=AIC_SVR16_ADC1IRQ
group.AIC.register.134=AIC_SVR17_DCA0IRQ
group.AIC.register.136=AIC_SVR18_DCA1IRQ
group.AIC.register.138=AIC_SVR19_RTCIRQ
group.AIC.register.140=AIC_SVR20_APMCIRQ
group.AIC.register.146=AIC_SVR23_IRQ6
group.AIC.register.148=AIC_SVR24_IRQ5
group.AIC.register.150=AIC_SVR25_IRQ4
group.AIC.register.152=AIC_SVR26_IRQ3
group.AIC.register.154=AIC_SVR27_IRQ2
group.AIC.register.156=AIC_SVR28_IRQ1
group.AIC.register.158=AIC_SVR29_IRQ0
group.AIC.register.160=AIC_SVR30_COMMTX
group.AIC.register.162=AIC_SVR31_COMMRX


group.AIC.register.200=AIC_IVR
group.AIC.register.202=AIC_FVR
group.AIC.register.204=AIC_ISR
group.AIC.register.206=AIC_IPR
group.AIC.register.208=AIC_IMR
group.AIC.register.210=AIC_CISR
group.AIC.register.212=AIC_IECR
group.AIC.register.214=AIC_IDCR
group.AIC.register.216=AIC_ICCR
group.AIC.register.218=AIC_ISCR
group.AIC.register.220=AIC_EOICR
group.AIC.register.222=AIC_SPU


##				AIC_SMR0_FIQ

AIC_SMR0_FIQ.width=32
AIC_SMR0_FIQ.access=memorymapped
AIC_SMR0_FIQ.address=AIC_BASE+0x00
AIC_SMR0_FIQ.byteEndian=little
AIC_SMR0_FIQ.type=bitfield

AIC_SMR0_FIQ.bits.0.name=PRIOR
AIC_SMR0_FIQ.bits.0.range=0..2
AIC_SMR0_FIQ.bits.0.type=enum
AIC_SMR0_FIQ.bits.0.enum.0.name=0 Lowest priority
AIC_SMR0_FIQ.bits.0.enum.1.name=1 priority
AIC_SMR0_FIQ.bits.0.enum.2.name=2 priority
AIC_SMR0_FIQ.bits.0.enum.3.name=3 priority
AIC_SMR0_FIQ.bits.0.enum.4.name=4 priority
AIC_SMR0_FIQ.bits.0.enum.5.name=5 priority
AIC_SMR0_FIQ.bits.0.enum.6.name=6 priority
AIC_SMR0_FIQ.bits.0.enum.7.name=7 Highest priority

AIC_SMR0_FIQ.bits.1.name=Reserved
AIC_SMR0_FIQ.bits.1.range=3..4

AIC_SMR0_FIQ.bits.2.name=SRCTYPE
AIC_SMR0_FIQ.bits.2.range=5..6
AIC_SMR0_FIQ.bits.2.type=enum
AIC_SMR0_FIQ.bits.2.enum.0.name=Low Level Sensitive
AIC_SMR0_FIQ.bits.2.enum.1.name=Negative Edge Triggered
AIC_SMR0_FIQ.bits.2.enum.2.name=High Level Sensitive
AIC_SMR0_FIQ.bits.2.enum.3.name=Positive Edge Triggered

AIC_SMR0_FIQ.bits.3.name=Reserved
AIC_SMR0_FIQ.bits.3.range=7..31


##				AIC_SMR1_SWIRQ

AIC_SMR1_SWIRQ.width=32
AIC_SMR1_SWIRQ.access=memorymapped
AIC_SMR1_SWIRQ.address=AIC_BASE+0x04
AIC_SMR1_SWIRQ.byteEndian=little
AIC_SMR1_SWIRQ.type=bitfield

AIC_SMR1_SWIRQ.bits.0.name=PRIOR
AIC_SMR1_SWIRQ.bits.0.range=0..2
AIC_SMR1_SWIRQ.bits.0.type=enum
AIC_SMR1_SWIRQ.bits.0.enum.0.name=0 Lowest priority
AIC_SMR1_SWIRQ.bits.0.enum.1.name=1 priority
AIC_SMR1_SWIRQ.bits.0.enum.2.name=2 priority
AIC_SMR1_SWIRQ.bits.0.enum.3.name=3 priority
AIC_SMR1_SWIRQ.bits.0.enum.4.name=4 priority
AIC_SMR1_SWIRQ.bits.0.enum.5.name=5 priority
AIC_SMR1_SWIRQ.bits.0.enum.6.name=6 priority
AIC_SMR1_SWIRQ.bits.0.enum.7.name=7 Highest priority

AIC_SMR1_SWIRQ.bits.1.name=Reserved
AIC_SMR1_SWIRQ.bits.1.range=3..4

AIC_SMR1_SWIRQ.bits.2.name=SRCTYPE
AIC_SMR1_SWIRQ.bits.2.range=5..6
AIC_SMR1_SWIRQ.bits.2.type=enum
AIC_SMR1_SWIRQ.bits.2.enum.0.name=Low Level Sensitive
AIC_SMR1_SWIRQ.bits.2.enum.1.name=Negative Edge Triggered
AIC_SMR1_SWIRQ.bits.2.enum.2.name=High Level Sensitive
AIC_SMR1_SWIRQ.bits.2.enum.3.name=Positive Edge Triggered

AIC_SMR1_SWIRQ.bits.3.name=Reserved
AIC_SMR1_SWIRQ.bits.3.range=7..31


##				AIC_SMR2_US0IRQ

AIC_SMR2_US0IRQ.width=32
AIC_SMR2_US0IRQ.access=memorymapped
AIC_SMR2_US0IRQ.address=AIC_BASE+0x08
AIC_SMR2_US0IRQ.byteEndian=little
AIC_SMR2_US0IRQ.type=bitfield

AIC_SMR2_US0IRQ.bits.0.name=PRIOR
AIC_SMR2_US0IRQ.bits.0.range=0..2
AIC_SMR2_US0IRQ.bits.0.type=enum
AIC_SMR2_US0IRQ.bits.0.enum.0.name=0 Lowest priority
AIC_SMR2_US0IRQ.bits.0.enum.1.name=1 priority
AIC_SMR2_US0IRQ.bits.0.enum.2.name=2 priority
AIC_SMR2_US0IRQ.bits.0.enum.3.name=3 priority
AIC_SMR2_US0IRQ.bits.0.enum.4.name=4 priority
AIC_SMR2_US0IRQ.bits.0.enum.5.name=5 priority
AIC_SMR2_US0IRQ.bits.0.enum.6.name=6 priority
AIC_SMR2_US0IRQ.bits.0.enum.7.name=7 Highest priority

AIC_SMR2_US0IRQ.bits.1.name=Reserved
AIC_SMR2_US0IRQ.bits.1.range=3..4

AIC_SMR2_US0IRQ.bits.2.name=SRCTYPE
AIC_SMR2_US0IRQ.bits.2.range=5..6
AIC_SMR2_US0IRQ.bits.2.type=enum
AIC_SMR2_US0IRQ.bits.2.enum.0.name=Low Level Sensitive
AIC_SMR2_US0IRQ.bits.2.enum.1.nam