at91_x55.rdf

基本的几个引用程序,来看卡发的有用程序,别错过了.

APMC_PMR.bits.3.range=4..4
APMC_PMR.bits.3.type=enum
APMC_PMR.bits.3.enum.0.name=no wakeup
APMC_PMR.bits.3.enum.1.name=wakeup
APMC_PMR.bits.4.name=WKACKS
APMC_PMR.bits.4.range=2..3
APMC_PMR.bits.4.type=enum
APMC_PMR.bits.4.enum.0.name=Tri-stated
APMC_PMR.bits.4.enum.1.name=Level 0 
APMC_PMR.bits.4.enum.2.name=Level 1 
APMC_PMR.bits.4.enum.3.name=Reserved 
APMC_PMR.bits.5.name=SHDALS
APMC_PMR.bits.5.range=0..1
APMC_PMR.bits.5.type=enum
APMC_PMR.bits.5.enum.0.name=Tri-stated
APMC_PMR.bits.5.enum.1.name=Level 0 
APMC_PMR.bits.5.enum.2.name=Level 1 
APMC_PMR.bits.5.enum.3.name=Reserved 

##                       APMC_SR

APMC_SR.name=APMC_SR
APMC_SR.width=32
APMC_SR.access=memorymapped
APMC_SR.address=APMC_BASE+0x30
APMC_SR.type=bitfield
APMC_SR.byteEndian=little
APMC_SR.permission.write=none
APMC_SR.bits.0.name=Reserved 
APMC_SR.bits.0.range=2..31
APMC_SR.bits.1.name=LOCK
APMC_SR.bits.1.range=1..1
APMC_SR.bits.1.type=enum
APMC_SR.bits.1.enum.0.name=PLL not stabilized
APMC_SR.bits.1.enum.1.name=PLL stabilized
APMC_SR.bits.2.name=MOSCS
APMC_SR.bits.2.range=0..0
APMC_SR.bits.2.type=enum
APMC_SR.bits.2.enum.0.name=Main Oscil not stabilized
APMC_SR.bits.2.enum.1.name=Main Oscil stabilized

##                       APMC_IER

APMC_IER.name=APMC_IER
APMC_IER.width=32
APMC_IER.access=memorymapped
APMC_IER.address=APMC_BASE+0x34
APMC_IER.type=bitfield
APMC_IER.byteEndian=little
APMC_IER.bits.0.name=Reserved
APMC_IER.bits.0.range=2..31
APMC_IER.bits.1.name=LOCK
APMC_IER.bits.1.range=1..1
APMC_IER.bits.1.type=enum
APMC_IER.bits.1.enum.0.name=Enable PLL Lock Interrupt *** Write Only ***
APMC_IER.bits.1.enum.1.name=Error: This register should always read zeros 
APMC_IER.bits.2.name=MOSCS
APMC_IER.bits.2.range=0..0
APMC_IER.bits.2.type=enum
APMC_IER.bits.2.enum.0.name=Enable Main Oscillator Interrupt *** Write Only ***
APMC_IER.bits.2.enum.1.name=Error: This register should always read zeros 

##                       APMC_IDR

APMC_IDR.name=APMC_IDR
APMC_IDR.width=32
APMC_IDR.access=memorymapped
APMC_IDR.address=APMC_BASE+0x38
APMC_IDR.type=bitfield
APMC_IDR.byteEndian=little
APMC_IDR.bits.0.name=Reserved
APMC_IDR.bits.0.range=2..31
APMC_IDR.bits.1.name=LOCK
APMC_IDR.bits.1.range=1..1
APMC_IDR.bits.1.type=enum
APMC_IDR.bits.1.enum.0.name=Disable PLL Lock Interrupt *** Write Only ***
APMC_IDR.bits.1.enum.1.name=Error: This register should always read zeros 
APMC_IDR.bits.2.name=MOSCS
APMC_IDR.bits.2.range=0..0
APMC_IDR.bits.2.type=enum
APMC_IDR.bits.2.enum.0.name=Disable Main Oscillator Interrupt *** Write Only ***
APMC_IDR.bits.2.enum.1.name=Error: This register should always read zeros 

##                       APMC_IMR

APMC_IMR.name=APMC_IMR
APMC_IMR.width=32
APMC_IMR.access=memorymapped
APMC_IMR.address=APMC_BASE+0x3C
APMC_IMR.type=bitfield
APMC_IMR.byteEndian=little
APMC_IMR.permission.write=none
APMC_IMR.bits.0.name=Reserved 
APMC_IMR.bits.0.range=2..31
APMC_IMR.bits.1.name=LOCK
APMC_IMR.bits.1.range=1..1
APMC_IMR.bits.1.type=enum
APMC_IMR.bits.1.enum.0.name=Main Oscil Interrupt Disabled
APMC_IMR.bits.1.enum.1.name=Main Oscil Interrupt Enabled
APMC_IMR.bits.2.name=MOSCS
APMC_IMR.bits.2.range=0..0
APMC_IMR.bits.2.type=enum
APMC_IMR.bits.2.enum.0.name=PLL Lock Interrupt Disabled
APMC_IMR.bits.2.enum.1.name=PLL Lock Interrupt Enabled

############################## RTC  ##############################

~define.RTC_BASE=0xFFFB8000

group.RTC.name=RTC: Real-time Clock

group.RTC.register.0=RTC_CR
group.RTC.register.2=RTC_MR
group.RTC.register.4=RTC_TIMR
group.RTC.register.6=RTC_CALR
group.RTC.register.8=RTC_TAR
group.RTC.register.10=RTC_CAR
group.RTC.register.12=RTC_SR
group.RTC.register.14=RTC_ICR
group.RTC.register.16=RTC_IER
group.RTC.register.18=RTC_IDR
group.RTC.register.20=RTC_IMR
group.RTC.register.22=RTC_VER

##                       RTC_CR

RTC_CR.name=RTC_CR
RTC_CR.width=32
RTC_CR.access=memorymapped
RTC_CR.address=RTC_BASE+0x0000
RTC_CR.type=bitfield
RTC_CR.byteEndian=little
RTC_CR.bits.0.name=Reserved
RTC_CR.bits.0.range=18..31
RTC_CR.bits.1.name=CEVSEL
RTC_CR.bits.1.range=16..17
RTC_CR.bits.1.type=enum
RTC_CR.bits.1.enum.0.name=Week change
RTC_CR.bits.1.enum.1.name=Month change
RTC_CR.bits.1.enum.2.name=Year change
RTC_CR.bits.1.enum.3.name=Year change
RTC_CR.bits.2.name=Reserved 
RTC_CR.bits.2.range=10..15
RTC_CR.bits.3.name=TEVSEL
RTC_CR.bits.3.range=8..9
RTC_CR.bits.3.type=enum
RTC_CR.bits.3.enum.0.name=Minute change
RTC_CR.bits.3.enum.1.name=Hour change
RTC_CR.bits.3.enum.2.name=Day change at Midnight
RTC_CR.bits.3.enum.3.name=Day change at Noon
RTC_CR.bits.4.name=Reserved
RTC_CR.bits.4.range=2..7
RTC_CR.bits.5.name=UPDCAL
RTC_CR.bits.5.range=1..1
RTC_CR.bits.5.type=enum
RTC_CR.bits.5.enum.0.name=No effect
RTC_CR.bits.5.enum.1.name=Disable Calendar counting
RTC_CR.bits.6.name=UPDTIM
RTC_CR.bits.6.range=0..0
RTC_CR.bits.6.type=enum
RTC_CR.bits.6.enum.0.name=No effect
RTC_CR.bits.6.enum.1.name=Disable Time counting

##                       RTC_MR

RTC_MR.name=RTC_MR
RTC_MR.width=32
RTC_MR.access=memorymapped
RTC_MR.address=RTC_BASE+0x0004
RTC_MR.type=bitfield
RTC_MR.byteEndian=little
RTC_MR.bits.0.name=Reserved
RTC_MR.bits.0.range=1..31
RTC_MR.bits.1.name=HRMOD
RTC_MR.bits.1.range=0..0
RTC_MR.bits.1.type=enum
RTC_MR.bits.1.enum.0.name=24-hour mode
RTC_MR.bits.1.enum.1.name=12-hour mode

##                       RTC_TIMR

RTC_TIMR.name=RTC_TIMR
RTC_TIMR.width=32
RTC_TIMR.access=memorymapped
RTC_TIMR.address=RTC_BASE+0x0008
RTC_TIMR.type=bitfield
RTC_TIMR.byteEndian=little
RTC_TIMR.bits.0.name=Reserved
RTC_TIMR.bits.0.range=23..31
RTC_TIMR.bits.1.name=AMPM
RTC_TIMR.bits.1.range=22..22
RTC_TIMR.bits.1.type=enum
RTC_TIMR.bits.1.enum.0.name=AM
RTC_TIMR.bits.1.enum.1.name=PM
RTC_TIMR.bits.2.name=HOUR
RTC_TIMR.bits.2.range=16..21
RTC_TIMR.bits.3.name=Reserved
RTC_TIMR.bits.3.range=15..15
RTC_TIMR.bits.4.name=MIN
RTC_TIMR.bits.4.range=8..14
RTC_TIMR.bits.5.name=Reserved
RTC_TIMR.bits.5.range=7..7
RTC_TIMR.bits.6.name=SEC
RTC_TIMR.bits.6.range=0..6

# RTC_TIMR ToDo:
# Create register definitions that display the values for MIN and SEC 

##                       RTC_CALR

RTC_CALR.name=RTC_CALR
RTC_CALR.width=32
RTC_CALR.access=memorymapped
RTC_CALR.address=RTC_BASE+0x000C
RTC_CALR.type=bitfield
RTC_CALR.byteEndian=little
RTC_CALR.bits.0.name=Reserved
RTC_CALR.bits.0.range=30..31
RTC_CALR.bits.1.name=DATE
RTC_CALR.bits.1.range=24..29
RTC_CALR.bits.2.name=DAY
RTC_CALR.bits.2.range=21..23
RTC_CALR.bits.3.name=MONTH
RTC_CALR.bits.3.range=16..20
RTC_CALR.bits.4.name=YEAR
RTC_CALR.bits.4.range=8..15
RTC_CALR.bits.5.name=Reserved
RTC_CALR.bits.5.range=6..7
RTC_CALR.bits.6.name=CENT
RTC_CALR.bits.6.range=0..5

# RTC_CALR ToDo:
# Create register definitions that display the proper values for all  

##                       RTC_TAR
RTC_TAR.name=RTC_TAR
RTC_TAR.width=32
RTC_TAR.access=memorymapped
RTC_TAR.address=RTC_BASE+0x0010
RTC_TAR.type=bitfield
RTC_TAR.byteEndian=little
RTC_TAR.bits.0.name=Reserved
RTC_TAR.bits.0.range=24..31
RTC_TAR.bits.1.name=HOUREN
RTC_TAR.bits.1.range=23..23
RTC_TAR.bits.1.type=enum
RTC_TAR.bits.1.enum.0.name=Hour alarm disabled
RTC_TAR.bits.1.enum.1.name=Hour alarm enabled
RTC_TAR.bits.2.name=AMPM
RTC_TAR.bits.2.range=22..22
RTC_TAR.bits.2.type=enum
RTC_TAR.bits.2.enum.0.name=AM
RTC_TAR.bits.2.enum.1.name=PM
RTC_TAR.bits.3.name=HOUR
RTC_TAR.bits.3.range=16..21
RTC_TAR.bits.4.name=MINEN
RTC_TAR.bits.4.range=15..15
RTC_TAR.bits.4.type=enum
RTC_TAR.bits.4.enum.0.name=Minute alarm disabled
RTC_TAR.bits.4.enum.1.name=Minute alarm enabled
RTC_TAR.bits.5.name=MIN
RTC_TAR.bits.5.range=8..14
RTC_TAR.bits.6.name=SECEN
RTC_TAR.bits.6.range=7..7
RTC_TAR.bits.6.type=enum
RTC_TAR.bits.6.enum.0.name=Second alarm disabled
RTC_TAR.bits.6.enum.1.name=Second alarm enabled
RTC_TAR.bits.7.name=SEC
RTC_TAR.bits.7.range=0..6

##                       RTC_CAR

RTC_CAR.name=RTC_CAR
RTC_CAR.width=32
RTC_CAR.access=memorymapped
RTC_CAR.address=RTC_BASE+0x0014
RTC_CAR.type=bitfield
RTC_CAR.byteEndian=little
RTC_CAR.bits.0.name=DATEEN
RTC_CAR.bits.0.range=31..31
RTC_CAR.bits.0.type=enum
RTC_CAR.bits.0.enum.0.name=Date alarm disabled
RTC_CAR.bits.0.enum.1.name=Date alarm enabled
RTC_CAR.bits.1.name=Reserved
RTC_CAR.bits.1.range=30..30
RTC_CAR.bits.2.name=DATE
RTC_CAR.bits.2.range=24..29
RTC_CAR.bits.3.name=MTHEN
RTC_CAR.bits.3.range=23..23
RTC_CAR.bits.3.type=enum
RTC_CAR.bits.3.enum.0.name=Month alarm disabled
RTC_CAR.bits.3.enum.1.name=Month alarm enabled
RTC_CAR.bits.4.name=Reserved 
RTC_CAR.bits.4.range=21..22
RTC_CAR.bits.5.name=MONTH
RTC_CAR.bits.5.range=16..20
RTC_CAR.bits.6.name=Reserved
RTC_CAR.bits.6.range=0..15

##                       RTC_SR

RTC_SR.name=RTC_SR
RTC_SR.width=32
RTC_SR.access=memorymapped
RTC_SR.address=RTC_BASE+0x0018
RTC_SR.type=bitfield
RTC_SR.byteEndian=little
RTC_SR.permission.write=none
RTC_SR.bits.0.name=Reserved
RTC_SR.bits.0.range=5..31
RTC_SR.bits.1.name=CALEV
RTC_SR.bits.1.range=4..4
RTC_SR.bits.1.type=enum
RTC_SR.bits.1.enum.0.name=No Cal Event
RTC_SR.bits.1.enum.1.name=Cal Event
RTC_SR.bits.2.name=TIMEV
RTC_SR.bits.2.range=3..3
RTC_SR.bits.2.type=enum
RTC_SR.bits.2.enum.0.name=No Time Event
RTC_SR.bits.2.enum.1.name=Time Event
RTC_SR.bits.3.name=SEC
RTC_SR.bits.3.range=2..2
RTC_SR.bits.3.type=enum
RTC_SR.bits.3.enum.0.name=No Sec Event
RTC_SR.bits.3.enum.1.name=Sec Event
RTC_SR.bits.4.name=ALARM
RTC_SR.bits.4.range=1..1
RTC_SR.bits.4.type=enum
RTC_SR.bits.4.enum.0.name=No Alarm
RTC_SR.bits.4.enum.1.name=Alarm
RTC_SR.bits.5.name=ACKUPD
RTC_SR.bits.5.range=0..0
RTC_SR.bits.5.type=enum
RTC_SR.bits.5.enum.0.name=Time/Cal regs locked
RTC_SR.bits.5.enum.1.name=Time/Cal regs unlocked

##                       RTC_ICR

RTC_ICR.name=RTC_ICR
RTC_ICR.width=32
RTC_ICR.access=memorymapped
RTC_ICR.address=RTC_BASE+0x001C
RTC_ICR.type=bitfield
RTC_ICR.byteEndian=little
RTC_ICR.bits.0.name=Reserved 
RTC_ICR.bits.0.range=5..31
RTC_ICR.bits.1.name=CALEV
RTC_ICR.bits.1.range=4..4
RTC_ICR.bits.1.type=enum
RTC_ICR.bits.1.enum.0.name=Clear Calendar Event bit *** Write Only ***
RTC_ICR.bits.1.enum.1.name=Error: This register should always read zeros 
RTC_ICR.bits.2.name=TIMEV
RTC_ICR.bits.2.range=3..3
RTC_ICR.bits.2.type=enum
RTC_ICR.bits.2.enum.0.name=Clear Time Event bit *** Write Only ***
RTC_ICR.bits.2.enum.1.name=Error: This register should always read zeros 
RTC_ICR.bits.3.name=SEC
RTC_ICR.bits.3.range=2..2
RTC_ICR.bits.3.type=enum
RTC_ICR.bits.3.enum.0.name=Clear Second Event bit *** Write Only ***
RTC_ICR.bits.3.enum.1.name=Error: This register should always read zeros 
RTC_ICR.bits.4.name=ALARM
RTC_ICR.bits.4.range=1..1
RTC_ICR.bits.4.type=enum
RTC_ICR.bits.4.enum.0.name=Clear Alarm Flag bit *** Write Only ***
RTC_ICR.bits.4.enum.1.name=Error: This register should always read zeros 
RTC_ICR.bits.5.name=ACKUPD
RTC_ICR.bits.5.range=0..0
RTC_ICR.bits.5.type=enum
RTC_ICR.bits.5.enum.0.name=Clear Acknowledge for Update status bit *** Write Only ***
RTC_ICR.bits.5.enum.1.name=Error: This register should always read zeros 

##                       RTC_IER

RTC_IER.name=RTC_IER
RTC_IER.width=32
RTC_IER.access=memorymapped
RTC_IER.address=RTC_BASE+0x0020
RTC_IER.type=bitfield
RTC_IER.byteEndian=little
RTC_IER.bits.0.name=Reserved
RTC_IER.bits.0.range=5..31
RTC_IER.bits.1.name=CALEV
RTC_IER.bits.1.range=4..4
RTC_IER.bits.1.type=enum
RTC_IER.bits.1.enum.0.name=Enable Calandar Event Interrupt *** Write Only ***
RTC_IER.bits.1.enum.1.name=Error: This register should always read zeros
RTC_IER.bits.2.name=TIMEV
RTC_IER.bits.2.range=3..3
RTC_IER.bits.2.type=enum
RTC_IER.bits.2.enum.0.name=Enable Time Event Interrupt *** Write Only ***
RTC_IER.bits.2.enum.1.name=Error: This register should always read zeros
RTC_IER.bits.3.name=SEC
RTC_IER.bits.3.range=2..2
RTC_IER.bits.3.type=enum
RTC_IER.bits.3.enum.0.name=Enable Second Event Interrupt *** Write Only ***
RTC_IER.bits.3.enum.1.name=Error: This register should always read zeros
RTC_IER.bits.4.name=ALARM
RTC_IER.bits.4.range=1..1
RTC_IER.bits.4.type=enum
RTC_IER.bits.4.enum.0.name=Enable Alarm Interrupt *** Write Only ***
RTC_IER.bits.4.enum.1.name=Error: This register should always read zeros
RTC_IER.bits.5.name=ACKUPD
RTC_IER.bits.5.range=0..0
RTC_IER.bits.5.type=enum
RTC_IER.bits.5.enum.0.name=Enable Acknowledge Update Interrupt *** Write Only ***