at91_x55.rdf

基本的几个引用程序,来看卡发的有用程序,别错过了.

APMC_SCDR.bits.1.name=CPU
APMC_SCDR.bits.1.range=0..0
APMC_SCDR.bits.1.type=enum
APMC_SCDR.bits.1.enum.0.name=DISABLE System Clock *** Write Only ***

##				APMC_SCSR
APMC_SCSR.width=32
APMC_SCSR.access=memorymapped
APMC_SCSR.address=APMC_BASE+0x08
APMC_SCSR.byteEndian=little
APMC_SCSR.type=bitfield
APMC_SCSR.permission.write=none

APMC_SCSR.bits.0.name=Reserved
APMC_SCSR.bits.0.range=1..31

APMC_SCSR.bits.1.name=CPU
APMC_SCSR.bits.1.range=0..0
APMC_SCSR.bits.1.type=enum 
APMC_SCSR.bits.1.enum.0.name=System clock is DISABLED
APMC_SCSR.bits.1.enum.1.name=System clock is ENABLED

##				APMC_PCER
APMC_PCER.width=32
APMC_PCER.access=memorymapped
APMC_PCER.address=APMC_BASE+0x10
APMC_PCER.byteEndian=little
APMC_PCER.type=bitfield
APMC_PCER.bits.0.name=Reserved
APMC_PCER.bits.0.range=19..31
APMC_PCER.bits.1.name=DAC1 
APMC_PCER.bits.1.range=18..18
APMC_PCER.bits.1.type=enum
APMC_PCER.bits.1.enum.0.name=Enable DAC1 *** Write Only ***
APMC_PCER.bits.1.enum.1.name=Error: This register should always read zeros  
APMC_PCER.bits.2.name=DAC0
APMC_PCER.bits.2.range=17..17
APMC_PCER.bits.2.type=enum
APMC_PCER.bits.2.enum.0.name=Enable DAC0 *** Write Only ***
APMC_PCER.bits.2.enum.1.name=Error: This register should always read zeros  
APMC_PCER.bits.3.name=ADC1
APMC_PCER.bits.3.range=16..16
APMC_PCER.bits.3.type=enum
APMC_PCER.bits.3.enum.0.name=Enable ADC1 *** Write Only ***
APMC_PCER.bits.3.enum.1.name=Error: This register should always read zeros  
APMC_PCER.bits.4.name=ADC0
APMC_PCER.bits.4.range=15..15
APMC_PCER.bits.4.type=enum
APMC_PCER.bits.4.enum.0.name=Enable ADC0 *** Write Only ***
APMC_PCER.bits.4.enum.1.name=Error: This register should always read zeros  
APMC_PCER.bits.5.name=PIOB
APMC_PCER.bits.5.range=14..14
APMC_PCER.bits.5.type=enum
APMC_PCER.bits.5.enum.0.name=Enable PIOB *** Write Only ***
APMC_PCER.bits.5.enum.1.name=Error: This register should always read zeros  
APMC_PCER.bits.6.name=PIOA
APMC_PCER.bits.6.range=13..13
APMC_PCER.bits.6.type=enum
APMC_PCER.bits.6.enum.0.name=Enable PIOA *** Write Only ***
APMC_PCER.bits.6.enum.1.name=Error: This register should always read zeros  
APMC_PCER.bits.7.name=Reserved
APMC_PCER.bits.7.range=12..12
APMC_PCER.bits.8.name=TC5
APMC_PCER.bits.8.range=11..11
APMC_PCER.bits.8.type=enum
APMC_PCER.bits.8.enum.0.name=Enable TC5 *** Write Only ***
APMC_PCER.bits.8.enum.1.name=Error: This register should always read zeros  
APMC_PCER.bits.9.name=TC4
APMC_PCER.bits.9.range=10..10
APMC_PCER.bits.9.type=enum
APMC_PCER.bits.9.enum.0.name=Enable TC4 *** Write Only ***
APMC_PCER.bits.9.enum.1.name=Error: This register should always read zeros  
APMC_PCER.bits.10.name=TC3
APMC_PCER.bits.10.range=9..9
APMC_PCER.bits.10.type=enum
APMC_PCER.bits.10.enum.0.name=Enable TC3 *** Write Only ***
APMC_PCER.bits.10.enum.1.name=Error: This register should always read zeros  
APMC_PCER.bits.11.name=TC2
APMC_PCER.bits.11.range=8..8
APMC_PCER.bits.11.type=enum
APMC_PCER.bits.11.enum.0.name=Enable TC2 *** Write Only ***
APMC_PCER.bits.11.enum.1.name=Error: This register should always read zeros  
APMC_PCER.bits.12.name=TC1
APMC_PCER.bits.12.range=7..7
APMC_PCER.bits.12.type=enum
APMC_PCER.bits.12.enum.0.name=Enable TC1 *** Write Only ***
APMC_PCER.bits.12.enum.1.name=Error: This register should always read zeros  
APMC_PCER.bits.13.name=TC0
APMC_PCER.bits.13.range=6..6
APMC_PCER.bits.13.type=enum
APMC_PCER.bits.13.enum.0.name=Enable TC0 *** Write Only ***
APMC_PCER.bits.13.enum.1.name=Error: This register should always read zeros  
APMC_PCER.bits.14.name=SPI
APMC_PCER.bits.14.range=5..5
APMC_PCER.bits.14.type=enum
APMC_PCER.bits.14.enum.0.name=Enable SPI *** Write Only ***
APMC_PCER.bits.14.enum.1.name=Error: This register should always read zeros  
APMC_PCER.bits.15.name=US2
APMC_PCER.bits.15.range=4..4
APMC_PCER.bits.15.type=enum
APMC_PCER.bits.15.enum.0.name=Enable US2 *** Write Only ***
APMC_PCER.bits.15.enum.1.name=Error: This register should always read zeros  
APMC_PCER.bits.16.name=US1
APMC_PCER.bits.16.range=3..3
APMC_PCER.bits.16.type=enum
APMC_PCER.bits.16.enum.0.name=Enable US1 *** Write Only ***
APMC_PCER.bits.16.enum.1.name=Error: This register should always read zeros  
APMC_PCER.bits.17.name=US0
APMC_PCER.bits.17.range=2..2
APMC_PCER.bits.17.type=enum
APMC_PCER.bits.17.enum.0.name=Enable US0 *** Write Only ***
APMC_PCER.bits.17.enum.1.name=Error: This register should always read zeros  
APMC_PCER.bits.18.name=Reserved
APMC_PCER.bits.18.range=0..1

##                       APMC_PCDR
APMC_PCDR.name=APMC_PCDR
APMC_PCDR.width=32
APMC_PCDR.access=memorymapped
APMC_PCDR.address=APMC_BASE+0x14
APMC_PCDR.type=bitfield
APMC_PCDR.byteEndian=little
APMC_PCDR.type=bitfield
APMC_PCDR.bits.0.name=Reserved
APMC_PCDR.bits.0.range=19..31
APMC_PCDR.bits.1.name=DAC1 
APMC_PCDR.bits.1.range=18..18
APMC_PCDR.bits.1.type=enum
APMC_PCDR.bits.1.enum.0.name=Disable DAC1 *** Write Only ***
APMC_PCDR.bits.1.enum.1.name=Error: This register should always read zeros  
APMC_PCDR.bits.2.name=DAC0
APMC_PCDR.bits.2.range=17..17
APMC_PCDR.bits.2.type=enum
APMC_PCDR.bits.2.enum.0.name=Disable DAC0 *** Write Only ***
APMC_PCDR.bits.2.enum.1.name=Error: This register should always read zeros  
APMC_PCDR.bits.3.name=ADC1
APMC_PCDR.bits.3.range=16..16
APMC_PCDR.bits.3.type=enum
APMC_PCDR.bits.3.enum.0.name=Disable ADC1 *** Write Only ***
APMC_PCDR.bits.3.enum.1.name=Error: This register should always read zeros  
APMC_PCDR.bits.4.name=ADC0
APMC_PCDR.bits.4.range=15..15
APMC_PCDR.bits.4.type=enum
APMC_PCDR.bits.4.enum.0.name=Disable ADC0 *** Write Only ***
APMC_PCDR.bits.4.enum.1.name=Error: This register should always read zeros  
APMC_PCDR.bits.5.name=PIOB
APMC_PCDR.bits.5.range=14..14
APMC_PCDR.bits.5.type=enum
APMC_PCDR.bits.5.enum.0.name=Disable PIOB *** Write Only ***
APMC_PCDR.bits.5.enum.1.name=Error: This register should always read zeros  
APMC_PCDR.bits.6.name=PIOA
APMC_PCDR.bits.6.range=13..13
APMC_PCDR.bits.6.type=enum
APMC_PCDR.bits.6.enum.0.name=Disable PIOA *** Write Only ***
APMC_PCDR.bits.6.enum.1.name=Error: This register should always read zeros  
APMC_PCDR.bits.7.name=Reserved
APMC_PCDR.bits.7.range=12..12
APMC_PCDR.bits.8.name=TC5
APMC_PCDR.bits.8.range=11..11
APMC_PCDR.bits.8.type=enum
APMC_PCDR.bits.8.enum.0.name=Disable TC5 *** Write Only ***
APMC_PCDR.bits.8.enum.1.name=Error: This register should always read zeros  
APMC_PCDR.bits.9.name=TC4
APMC_PCDR.bits.9.range=10..10
APMC_PCDR.bits.9.type=enum
APMC_PCDR.bits.9.enum.0.name=Disable TC4 *** Write Only ***
APMC_PCDR.bits.9.enum.1.name=Error: This register should always read zeros  
APMC_PCDR.bits.10.name=TC3
APMC_PCDR.bits.10.range=9..9
APMC_PCDR.bits.10.type=enum
APMC_PCDR.bits.10.enum.0.name=Disable TC3 *** Write Only ***
APMC_PCDR.bits.10.enum.1.name=Error: This register should always read zeros  
APMC_PCDR.bits.11.name=TC2
APMC_PCDR.bits.11.range=8..8
APMC_PCDR.bits.11.type=enum
APMC_PCDR.bits.11.enum.0.name=Disable TC2 *** Write Only ***
APMC_PCDR.bits.11.enum.1.name=Error: This register should always read zeros  
APMC_PCDR.bits.12.name=TC1
APMC_PCDR.bits.12.range=7..7
APMC_PCDR.bits.12.type=enum
APMC_PCDR.bits.12.enum.0.name=Disable TC1 *** Write Only ***
APMC_PCDR.bits.12.enum.1.name=Error: This register should always read zeros  
APMC_PCDR.bits.13.name=TC0
APMC_PCDR.bits.13.range=6..6
APMC_PCDR.bits.13.type=enum
APMC_PCDR.bits.13.enum.0.name=Disable TC0 *** Write Only ***
APMC_PCDR.bits.13.enum.1.name=Error: This register should always read zeros  
APMC_PCDR.bits.14.name=SPI
APMC_PCDR.bits.14.range=5..5
APMC_PCDR.bits.14.type=enum
APMC_PCDR.bits.14.enum.0.name=Disable SPI *** Write Only ***
APMC_PCDR.bits.14.enum.1.name=Error: This register should always read zeros  
APMC_PCDR.bits.15.name=US2
APMC_PCDR.bits.15.range=4..4
APMC_PCDR.bits.15.type=enum
APMC_PCDR.bits.15.enum.0.name=Disable US2 *** Write Only ***
APMC_PCDR.bits.15.enum.1.name=Error: This register should always read zeros  
APMC_PCDR.bits.16.name=US1
APMC_PCDR.bits.16.range=3..3
APMC_PCDR.bits.16.type=enum
APMC_PCDR.bits.16.enum.0.name=Disable US1 *** Write Only ***
APMC_PCDR.bits.16.enum.1.name=Error: This register should always read zeros  
APMC_PCDR.bits.17.name=US0
APMC_PCDR.bits.17.range=2..2
APMC_PCDR.bits.17.type=enum
APMC_PCDR.bits.17.enum.0.name=Disable US0 *** Write Only ***
APMC_PCDR.bits.17.enum.1.name=Error: This register should always read zeros  
APMC_PCDR.bits.18.name=Reserved
APMC_PCDR.bits.18.range=0..1

##                       APMC_PCSR
APMC_PCSR.name=APMC_PCSR
APMC_PCSR.width=32
APMC_PCSR.access=memorymapped
APMC_PCSR.address=APMC_BASE+0x18
APMC_PCSR.permission.write=none
APMC_PCSR.type=bitfield
APMC_PCSR.byteEndian=little
APMC_PCSR.type=bitfield
APMC_PCSR.bits.0.name=Reserved
APMC_PCSR.bits.0.range=19..31
APMC_PCSR.bits.1.name=DAC1 
APMC_PCSR.bits.1.range=18..18
APMC_PCSR.bits.1.type=enum
APMC_PCSR.bits.1.enum.0.name=DAC1 Disabled
APMC_PCSR.bits.1.enum.1.name=DAC1 Enabled
APMC_PCSR.bits.2.name=DAC0
APMC_PCSR.bits.2.range=17..17
APMC_PCSR.bits.2.type=enum
APMC_PCSR.bits.2.enum.0.name=DAC0 Disabled
APMC_PCSR.bits.2.enum.1.name=DAC0 Enabled
APMC_PCSR.bits.3.name=ADC1
APMC_PCSR.bits.3.range=16..16
APMC_PCSR.bits.3.type=enum
APMC_PCSR.bits.3.enum.0.name=ADC1 Disabled
APMC_PCSR.bits.3.enum.1.name=ADC1 Enabled
APMC_PCSR.bits.4.name=ADC0
APMC_PCSR.bits.4.range=15..15
APMC_PCSR.bits.4.type=enum
APMC_PCSR.bits.4.enum.0.name=ADC0 Disabled
APMC_PCSR.bits.4.enum.1.name=ADC0 Enabled
APMC_PCSR.bits.5.name=PIOB
APMC_PCSR.bits.5.range=14..14
APMC_PCSR.bits.5.type=enum
APMC_PCSR.bits.5.enum.0.name=PIOB Disabled
APMC_PCSR.bits.5.enum.1.name=PIOB Enabled
APMC_PCSR.bits.6.name=PIOA
APMC_PCSR.bits.6.range=13..13
APMC_PCSR.bits.6.type=enum
APMC_PCSR.bits.6.enum.0.name=PIOA Disabled
APMC_PCSR.bits.6.enum.1.name=PIOA Enabled
APMC_PCSR.bits.7.name=Reserved
APMC_PCSR.bits.7.range=12..12
APMC_PCSR.bits.8.name=TC5
APMC_PCSR.bits.8.range=11..11
APMC_PCSR.bits.8.type=enum
APMC_PCSR.bits.8.enum.0.name=TC5 Disabled
APMC_PCSR.bits.8.enum.1.name=TC5 Enabled
APMC_PCSR.bits.9.name=TC4
APMC_PCSR.bits.9.range=10..10
APMC_PCSR.bits.9.type=enum
APMC_PCSR.bits.9.enum.0.name=TC4 Disabled
APMC_PCSR.bits.9.enum.1.name=TC4 Enabled
APMC_PCSR.bits.10.name=TC3
APMC_PCSR.bits.10.range=9..9
APMC_PCSR.bits.10.type=enum
APMC_PCSR.bits.10.enum.0.name=TC3 Disabled
APMC_PCSR.bits.10.enum.1.name=TC3 Enabled
APMC_PCSR.bits.11.name=TC2
APMC_PCSR.bits.11.range=8..8
APMC_PCSR.bits.11.type=enum
APMC_PCSR.bits.11.enum.0.name=TC2 Disabled
APMC_PCSR.bits.11.enum.1.name=TC2 Enabled
APMC_PCSR.bits.12.name=TC1
APMC_PCSR.bits.12.range=7..7
APMC_PCSR.bits.12.type=enum
APMC_PCSR.bits.12.enum.0.name=TC1 Disabled
APMC_PCSR.bits.12.enum.1.name=TC1 Enabled
APMC_PCSR.bits.13.name=TC0
APMC_PCSR.bits.13.range=6..6
APMC_PCSR.bits.13.type=enum
APMC_PCSR.bits.13.enum.0.name=TC0 Disabled
APMC_PCSR.bits.13.enum.1.name=TC0 Enabled
APMC_PCSR.bits.14.name=SPI
APMC_PCSR.bits.14.range=5..5
APMC_PCSR.bits.14.type=enum
APMC_PCSR.bits.14.enum.0.name=SPI Disabled
APMC_PCSR.bits.14.enum.1.name=SPI Enabled
APMC_PCSR.bits.15.name=US2
APMC_PCSR.bits.15.range=4..4
APMC_PCSR.bits.15.type=enum
APMC_PCSR.bits.15.enum.0.name=US2 Disabled
APMC_PCSR.bits.15.enum.1.name=US2 Enabled
APMC_PCSR.bits.16.name=US1
APMC_PCSR.bits.16.range=3..3
APMC_PCSR.bits.16.type=enum
APMC_PCSR.bits.16.enum.0.name=US1 Disabled
APMC_PCSR.bits.16.enum.1.name=US1 Enabled
APMC_PCSR.bits.17.name=US0
APMC_PCSR.bits.17.range=2..2
APMC_PCSR.bits.17.type=enum
APMC_PCSR.bits.17.enum.0.name=US0 Disabled
APMC_PCSR.bits.17.enum.1.name=US0 Enabled
APMC_PCSR.bits.18.name=Reserved
APMC_PCSR.bits.18.range=0..1

##                       APMC_CGMR
APMC_CGMR.name=APMC_CGMR
APMC_CGMR.width=32
APMC_CGMR.access=memorymapped
APMC_CGMR.address=APMC_BASE+0x20
APMC_CGMR.type=bitfield
APMC_CGMR.byteEndian=little
APMC_CGMR.bits.0.name=Reserved
APMC_CGMR.bits.0.range=30..31
APMC_CGMR.bits.1.name=PLLCOUNT
APMC_CGMR.bits.1.range=24..29
APMC_CGMR.bits.2.name=OSCOUNT
APMC_CGMR.bits.2.range=16..23
APMC_CGMR.bits.3.name=CSS
APMC_CGMR.bits.3.range=14..15
APMC_CGMR.bits.3.type=enum
APMC_CGMR.bits.3.enum.0.name=Low-freq clk 
APMC_CGMR.bits.3.enum.1.name=Main oscil or extern clk
APMC_CGMR.bits.3.enum.2.name=Phase Lock Loop
APMC_CGMR.bits.3.enum.3.name=Reserved
APMC_CGMR.bits.4.name=MUL
APMC_CGMR.bits.4.range=8..13
APMC_CGMR.bits.5.name=Reserved
APMC_CGMR.bits.5.range=7..7
APMC_CGMR.bits.6.name=PRES
APMC_CGMR.bits.6.range=4..6
APMC_CGMR.bits.6.type=enum
APMC_CGMR.bits.6.enum.0.name=clock output
APMC_CGMR.bits.6.enum.1.name=divided by 2
APMC_CGMR.bits.6.enum.2.name=divided by 4
APMC_CGMR.bits.6.enum.3.name=divided by 8
APMC_CGMR.bits.6.enum.4.name=divided by 16
APMC_CGMR.bits.6.enum.5.name=divided by 32
APMC_CGMR.bits.6.enum.6.name=divided by 64
APMC_CGMR.bits.6.enum.7.name=Reserved 
APMC_CGMR.bits.7.name=Reserved
APMC_CGMR.bits.7.range=3..3
APMC_CGMR.bits.8.name=MCKODS
APMC_CGMR.bits.8.range=2..2
APMC_CGMR.bits.3.type=enum
APMC_CGMR.bits.3.enum.0.name=Master Clock
APMC_CGMR.bits.3.enum.1.name=Tri-stated
APMC_CGMR.bits.9.name=MOSCEN
APMC_CGMR.bits.9.range=1..1
APMC_CGMR.bits.3.type=enum
APMC_CGMR.bits.3.enum.0.name=disabled
APMC_CGMR.bits.3.enum.1.name=enabled
APMC_CGMR.bits.10.name=MOSCBYP
APMC_CGMR.bits.10.range=0..0
APMC_CGMR.bits.10.type=enum
APMC_CGMR.bits.10.enum.0.name=XIN-Crystal-XOUT
APMC_CGMR.bits.10.enum.1.name=XIN-Extern Clock

# APMC_CGMR ToDo:
# Register to calculate values for OSCOUNT and PLLCOUNT periods

##                       APMC_PCR

APMC_PCR.name=APMC_PCR
APMC_PCR.width=32
APMC_PCR.access=memorymapped
APMC_PCR.address=APMC_BASE+0x28
APMC_PCR.type=bitfield
APMC_PCR.byteEndian=little
APMC_PCR.bits.0.name=Reserved
APMC_PCR.bits.0.range=2..31
APMC_PCR.bits.1.name=WKACKC
APMC_PCR.bits.1.range=1..1
APMC_PCR.bits.1.type=enum
APMC_PCR.bits.1.enum.0.name=WKACKS in APMC_PMR defines SHDN pin *** Write Only ***
APMC_PCR.bits.1.enum.1.name=Error: This register should always read zeros 
APMC_PCR.bits.2.name=SHDALC
APMC_PCR.bits.2.range=0..0
APMC_PCR.bits.2.type=enum
APMC_PCR.bits.2.enum.0.name=SHDALS in APMC_PMR defines SHDN pin *** Write Only ***
APMC_PCR.bits.2.enum.1.name=Error: This register should always read zeros 

##                       APMC_PMR

APMC_PMR.name=APMC_PMR
APMC_PMR.width=32
APMC_PMR.access=memorymapped
APMC_PMR.address=APMC_BASE+0x2C
APMC_PMR.type=bitfield
APMC_PMR.byteEndian=little
APMC_PMR.bits.0.name=Reserved
APMC_PMR.bits.0.range=8..31
APMC_PMR.bits.1.name=WKEDG
APMC_PMR.bits.1.range=6..7
APMC_PMR.bits.1.type=enum
APMC_PMR.bits.1.enum.0.name=None
APMC_PMR.bits.1.enum.1.name=Positive edge
APMC_PMR.bits.1.enum.2.name=Negative edge
APMC_PMR.bits.1.enum.3.name=Both edges
APMC_PMR.bits.2.name=ALSHEN 
APMC_PMR.bits.2.range=5..5
APMC_PMR.bits.2.type=enum
APMC_PMR.bits.2.enum.0.name=no shutdown 
APMC_PMR.bits.2.enum.1.name=shutdown 
APMC_PMR.bits.3.name=ALWKEN