at91_x55.rdf

基本的几个引用程序,来看卡发的有用程序,别错过了.

##                       EBI_CSR4

#EBI_CSR4
EBI_CSR4.width=32
EBI_CSR4.access=memorymapped
EBI_CSR4.address=EBI_BASE+0x10 
EBI_CSR4.byteEndian=little
EBI_CSR4.type=bitfield

EBI_CSR4.bits.0.name=DBW
EBI_CSR4.bits.0.range=0..1
EBI_CSR4.bits.0.type=enum
EBI_CSR4.bits.0.enum.0.name=Reserved
EBI_CSR4.bits.0.enum.1.name=16 bit data bus width
EBI_CSR4.bits.0.enum.2.name=8 bit data bus width
EBI_CSR4.bits.0.enum.3.name=Reserved

EBI_CSR4.bits.1.name=WS
EBI_CSR4.bits.1.range=2..4
EBI_CSR4.bits.1.type=enum
EBI_CSR4.bits.1.enum.0.name=1 Wait State
EBI_CSR4.bits.1.enum.1.name=2 Wait States
EBI_CSR4.bits.1.enum.2.name=3 Wait States
EBI_CSR4.bits.1.enum.3.name=4 Wait States
EBI_CSR4.bits.1.enum.4.name=5 Wait States
EBI_CSR4.bits.1.enum.5.name=6 Wait States
EBI_CSR4.bits.1.enum.6.name=7 Wait States
EBI_CSR4.bits.1.enum.7.name=8 Wait States

EBI_CSR4.bits.2.name=WSE
EBI_CSR4.bits.2.range=5..5
EBI_CSR4.bits.2.type=enum
EBI_CSR4.bits.2.enum.0.name=Disable Wait States
EBI_CSR4.bits.2.enum.1.name=Enable Wait States

EBI_CSR4.bits.3.name=Reserved
EBI_CSR4.bits.3.range=6..6

EBI_CSR4.bits.4.name=PAGES
EBI_CSR4.bits.4.range=7..8
EBI_CSR4.bits.4.type=enum
EBI_CSR4.bits.4.enum.0.name=1 MB Page Size
EBI_CSR4.bits.4.enum.1.name=4 MB Page Size
EBI_CSR4.bits.4.enum.2.name=16 MB Page Size
EBI_CSR4.bits.4.enum.3.name=64 MB Page Size

EBI_CSR4.bits.5.name=TDF
EBI_CSR4.bits.5.range=9..11
EBI_CSR4.bits.5.type=enum
EBI_CSR4.bits.5.enum.0.name=0 Cycles after transfer
EBI_CSR4.bits.5.enum.1.name=1 Cycles after transfer
EBI_CSR4.bits.5.enum.2.name=2 Cycles after transfer
EBI_CSR4.bits.5.enum.3.name=3 Cycles after transfer
EBI_CSR4.bits.5.enum.4.name=4 Cycles after transfer
EBI_CSR4.bits.5.enum.5.name=5 Cycles after transfer
EBI_CSR4.bits.5.enum.6.name=6 Cycles after transfer
EBI_CSR4.bits.5.enum.7.name=7 Cycles after transfer

EBI_CSR4.bits.6.name=BAT
EBI_CSR4.bits.6.range=12..12
EBI_CSR4.bits.6.type=enum
EBI_CSR4.bits.6.enum.0.name=Byte-Write access
EBI_CSR4.bits.6.enum.1.name=Byte-Select access

EBI_CSR4.bits.7.name=CSEN
EBI_CSR4.bits.7.range=13..13
EBI_CSR4.bits.7.type=enum
EBI_CSR4.bits.7.enum.0.name=Chip Select Disabled
EBI_CSR4.bits.7.enum.1.name=Chip Select Enabled

EBI_CSR4.bits.8.name=WP
EBI_CSR4.bits.8.range=14..14
EBI_CSR4.bits.8.type=enum
EBI_CSR4.bits.8.enum.0.name=Not Write Protected
EBI_CSR4.bits.8.enum.1.name=Write Protected

EBI_CSR4.bits.9.name=Reserved
EBI_CSR4.bits.9.range=15..19

EBI_CSR4.bits.10.name=BA
EBI_CSR4.bits.10.range=20..31

##                       EBI_CSR5

#EBI_CSR5
EBI_CSR5.width=32
EBI_CSR5.access=memorymapped
EBI_CSR5.address=EBI_BASE+0x14 
EBI_CSR5.byteEndian=little
EBI_CSR5.type=bitfield

EBI_CSR5.bits.0.name=DBW
EBI_CSR5.bits.0.range=0..1
EBI_CSR5.bits.0.type=enum
EBI_CSR5.bits.0.enum.0.name=Reserved
EBI_CSR5.bits.0.enum.1.name=16 bit data bus width
EBI_CSR5.bits.0.enum.2.name=8 bit data bus width
EBI_CSR5.bits.0.enum.3.name=Reserved

EBI_CSR5.bits.1.name=WS
EBI_CSR5.bits.1.range=2..4
EBI_CSR5.bits.1.type=enum
EBI_CSR5.bits.1.enum.0.name=1 Wait State
EBI_CSR5.bits.1.enum.1.name=2 Wait States
EBI_CSR5.bits.1.enum.2.name=3 Wait States
EBI_CSR5.bits.1.enum.3.name=4 Wait States
EBI_CSR5.bits.1.enum.4.name=5 Wait States
EBI_CSR5.bits.1.enum.5.name=6 Wait States
EBI_CSR5.bits.1.enum.6.name=7 Wait States
EBI_CSR5.bits.1.enum.7.name=8 Wait States

EBI_CSR5.bits.2.name=WSE
EBI_CSR5.bits.2.range=5..5
EBI_CSR5.bits.2.type=enum
EBI_CSR5.bits.2.enum.0.name=Disable Wait States
EBI_CSR5.bits.2.enum.1.name=Enable Wait States

EBI_CSR5.bits.3.name=Reserved
EBI_CSR5.bits.3.range=6..6

EBI_CSR5.bits.4.name=PAGES
EBI_CSR5.bits.4.range=7..8
EBI_CSR5.bits.4.type=enum
EBI_CSR5.bits.4.enum.0.name=1 MB Page Size
EBI_CSR5.bits.4.enum.1.name=4 MB Page Size
EBI_CSR5.bits.4.enum.2.name=16 MB Page Size
EBI_CSR5.bits.4.enum.3.name=64 MB Page Size

EBI_CSR5.bits.5.name=TDF
EBI_CSR5.bits.5.range=9..11
EBI_CSR5.bits.5.type=enum
EBI_CSR5.bits.5.enum.0.name=0 Cycles after transfer
EBI_CSR5.bits.5.enum.1.name=1 Cycles after transfer
EBI_CSR5.bits.5.enum.2.name=2 Cycles after transfer
EBI_CSR5.bits.5.enum.3.name=3 Cycles after transfer
EBI_CSR5.bits.5.enum.4.name=4 Cycles after transfer
EBI_CSR5.bits.5.enum.5.name=5 Cycles after transfer
EBI_CSR5.bits.5.enum.6.name=6 Cycles after transfer
EBI_CSR5.bits.5.enum.7.name=7 Cycles after transfer

EBI_CSR5.bits.6.name=BAT
EBI_CSR5.bits.6.range=12..12
EBI_CSR5.bits.6.type=enum
EBI_CSR5.bits.6.enum.0.name=Byte-Write access
EBI_CSR5.bits.6.enum.1.name=Byte-Select access

EBI_CSR5.bits.7.name=CSEN
EBI_CSR5.bits.7.range=13..13
EBI_CSR5.bits.7.type=enum
EBI_CSR5.bits.7.enum.0.name=Chip Select Disabled
EBI_CSR5.bits.7.enum.1.name=Chip Select Enabled

EBI_CSR5.bits.8.name=WP
EBI_CSR5.bits.8.range=14..14
EBI_CSR5.bits.8.type=enum
EBI_CSR5.bits.8.enum.0.name=Not Write Protected
EBI_CSR5.bits.8.enum.1.name=Write Protected

EBI_CSR5.bits.9.name=Reserved
EBI_CSR5.bits.9.range=15..19

EBI_CSR5.bits.10.name=BA
EBI_CSR5.bits.10.range=20..31

##                       EBI_CSR6

#EBI_CSR6
EBI_CSR6.width=32
EBI_CSR6.access=memorymapped
EBI_CSR6.address=EBI_BASE+0x18 
EBI_CSR6.byteEndian=little
EBI_CSR6.type=bitfield

EBI_CSR6.bits.0.name=DBW
EBI_CSR6.bits.0.range=0..1
EBI_CSR6.bits.0.type=enum
EBI_CSR6.bits.0.enum.0.name=Reserved
EBI_CSR6.bits.0.enum.1.name=16 bit data bus width
EBI_CSR6.bits.0.enum.2.name=8 bit data bus width
EBI_CSR6.bits.0.enum.3.name=Reserved

EBI_CSR6.bits.1.name=WS
EBI_CSR6.bits.1.range=2..4
EBI_CSR6.bits.1.type=enum
EBI_CSR6.bits.1.enum.0.name=1 Wait State
EBI_CSR6.bits.1.enum.1.name=2 Wait States
EBI_CSR6.bits.1.enum.2.name=3 Wait States
EBI_CSR6.bits.1.enum.3.name=4 Wait States
EBI_CSR6.bits.1.enum.4.name=5 Wait States
EBI_CSR6.bits.1.enum.5.name=6 Wait States
EBI_CSR6.bits.1.enum.6.name=7 Wait States
EBI_CSR6.bits.1.enum.7.name=8 Wait States

EBI_CSR6.bits.2.name=WSE
EBI_CSR6.bits.2.range=5..5
EBI_CSR6.bits.2.type=enum
EBI_CSR6.bits.2.enum.0.name=Disable Wait States
EBI_CSR6.bits.2.enum.1.name=Enable Wait States

EBI_CSR6.bits.3.name=Reserved
EBI_CSR6.bits.3.range=6..6

EBI_CSR6.bits.4.name=PAGES
EBI_CSR6.bits.4.range=7..8
EBI_CSR6.bits.4.type=enum
EBI_CSR6.bits.4.enum.0.name=1 MB Page Size
EBI_CSR6.bits.4.enum.1.name=4 MB Page Size
EBI_CSR6.bits.4.enum.2.name=16 MB Page Size
EBI_CSR6.bits.4.enum.3.name=64 MB Page Size

EBI_CSR6.bits.5.name=TDF
EBI_CSR6.bits.5.range=9..11
EBI_CSR6.bits.5.type=enum
EBI_CSR6.bits.5.enum.0.name=0 Cycles after transfer
EBI_CSR6.bits.5.enum.1.name=1 Cycles after transfer
EBI_CSR6.bits.5.enum.2.name=2 Cycles after transfer
EBI_CSR6.bits.5.enum.3.name=3 Cycles after transfer
EBI_CSR6.bits.5.enum.4.name=4 Cycles after transfer
EBI_CSR6.bits.5.enum.5.name=5 Cycles after transfer
EBI_CSR6.bits.5.enum.6.name=6 Cycles after transfer
EBI_CSR6.bits.5.enum.7.name=7 Cycles after transfer

EBI_CSR6.bits.6.name=BAT
EBI_CSR6.bits.6.range=12..12
EBI_CSR6.bits.6.type=enum
EBI_CSR6.bits.6.enum.0.name=Byte-Write access
EBI_CSR6.bits.6.enum.1.name=Byte-Select access

EBI_CSR6.bits.7.name=CSEN
EBI_CSR6.bits.7.range=13..13
EBI_CSR6.bits.7.type=enum
EBI_CSR6.bits.7.enum.0.name=Chip Select Disabled
EBI_CSR6.bits.7.enum.1.name=Chip Select Enabled

EBI_CSR6.bits.8.name=WP
EBI_CSR6.bits.8.range=14..14
EBI_CSR6.bits.8.type=enum
EBI_CSR6.bits.8.enum.0.name=Not Write Protected
EBI_CSR6.bits.8.enum.1.name=Write Protected

EBI_CSR6.bits.9.name=Reserved
EBI_CSR6.bits.9.range=15..19

EBI_CSR6.bits.10.name=BA
EBI_CSR6.bits.10.range=20..31

##                       EBI_CSR7

#EBI_CSR7
EBI_CSR7.width=32
EBI_CSR7.access=memorymapped
EBI_CSR7.address=EBI_BASE+0x1c 
EBI_CSR7.byteEndian=little
EBI_CSR7.type=bitfield

EBI_CSR7.bits.0.name=DBW
EBI_CSR7.bits.0.range=0..1
EBI_CSR7.bits.0.type=enum
EBI_CSR7.bits.0.enum.0.name=Reserved
EBI_CSR7.bits.0.enum.1.name=16 bit data bus width
EBI_CSR7.bits.0.enum.2.name=8 bit data bus width
EBI_CSR7.bits.0.enum.3.name=Reserved

EBI_CSR7.bits.1.name=WS
EBI_CSR7.bits.1.range=2..4
EBI_CSR7.bits.1.type=enum
EBI_CSR7.bits.1.enum.0.name=1 Wait State
EBI_CSR7.bits.1.enum.1.name=2 Wait States
EBI_CSR7.bits.1.enum.2.name=3 Wait States
EBI_CSR7.bits.1.enum.3.name=4 Wait States
EBI_CSR7.bits.1.enum.4.name=5 Wait States
EBI_CSR7.bits.1.enum.5.name=6 Wait States
EBI_CSR7.bits.1.enum.6.name=7 Wait States
EBI_CSR7.bits.1.enum.7.name=8 Wait States

EBI_CSR7.bits.2.name=WSE
EBI_CSR7.bits.2.range=5..5
EBI_CSR7.bits.2.type=enum
EBI_CSR7.bits.2.enum.0.name=Disable Wait States
EBI_CSR7.bits.2.enum.1.name=Enable Wait States

EBI_CSR7.bits.3.name=Reserved
EBI_CSR7.bits.3.range=6..6

EBI_CSR7.bits.4.name=PAGES
EBI_CSR7.bits.4.range=7..8
EBI_CSR7.bits.4.type=enum
EBI_CSR7.bits.4.enum.0.name=1 MB Page Size
EBI_CSR7.bits.4.enum.1.name=4 MB Page Size
EBI_CSR7.bits.4.enum.2.name=16 MB Page Size
EBI_CSR7.bits.4.enum.3.name=64 MB Page Size

EBI_CSR7.bits.5.name=TDF
EBI_CSR7.bits.5.range=9..11
EBI_CSR7.bits.5.type=enum
EBI_CSR7.bits.5.enum.0.name=0 Cycles after transfer
EBI_CSR7.bits.5.enum.1.name=1 Cycles after transfer
EBI_CSR7.bits.5.enum.2.name=2 Cycles after transfer
EBI_CSR7.bits.5.enum.3.name=3 Cycles after transfer
EBI_CSR7.bits.5.enum.4.name=4 Cycles after transfer
EBI_CSR7.bits.5.enum.5.name=5 Cycles after transfer
EBI_CSR7.bits.5.enum.6.name=6 Cycles after transfer
EBI_CSR7.bits.5.enum.7.name=7 Cycles after transfer

EBI_CSR7.bits.6.name=BAT
EBI_CSR7.bits.6.range=12..12
EBI_CSR7.bits.6.type=enum
EBI_CSR7.bits.6.enum.0.name=Byte-Write access
EBI_CSR7.bits.6.enum.1.name=Byte-Select access

EBI_CSR7.bits.7.name=CSEN
EBI_CSR7.bits.7.range=13..13
EBI_CSR7.bits.7.type=enum
EBI_CSR7.bits.7.enum.0.name=Chip Select Disabled
EBI_CSR7.bits.7.enum.1.name=Chip Select Enabled

EBI_CSR7.bits.8.name=WP
EBI_CSR7.bits.8.range=14..14
EBI_CSR7.bits.8.type=enum
EBI_CSR7.bits.8.enum.0.name=Not Write Protected
EBI_CSR7.bits.8.enum.1.name=Write Protected

EBI_CSR7.bits.9.name=Reserved
EBI_CSR7.bits.9.range=15..19

EBI_CSR7.bits.10.name=BA
EBI_CSR7.bits.10.range=20..31


##                       EBI_RCR
EBI_RCR.width=32
EBI_RCR.access=memorymapped
EBI_RCR.address=EBI_BASE+0x20
EBI_RCR.byteEndian=little
EBI_RCR.type=bitfield
EBI_RCR.bits.0.name=RCB
EBI_RCR.bits.0.range=0..0
EBI_RCR.bits.0.type=enum
EBI_RCR.bits.0.enum.0.name=Cancel remapping of page zero memory devices *** Write only ***
EBI_RCR.bits.0.enum.1.name=Error: This register should always read zeros 
EBI_RCR.bits.1.name=Reserved
EBI_RCR.bits.1.range=1..31

##                       EBI_MCR
EBI_MCR.width=32
EBI_MCR.access=memorymapped
EBI_MCR.address=EBI_BASE+0x24
EBI_MCR.byteEndian=little
EBI_MCR.type=bitfield
EBI_MCR.bits.0.name=Reserved
EBI_MCR.bits.0.range=5..31
EBI_MCR.bits.1.name=DRP
EBI_MCR.bits.1.range=4..4
EBI_MCR.bits.1.type=enum
EBI_MCR.bits.1.enum.0.name=Standard read protocol for all external memory devices enabled
EBI_MCR.bits.1.enum.1.name=Early read protocol for all external memory devices enabled
EBI_MCR.bits.2.name=Reserved
EBI_MCR.bits.2.range=0..3

############################## APMC ##############################

~define.APMC_BASE=0xFFFF4000

group.APMC.name=APMC: Advanced Power Management Controller

group.APMC.register.0=APMC_SCER
group.APMC.register.2=APMC_SCDR
group.APMC.register.4=APMC_SCSR
group.APMC.register.6=APMC_PCER
group.APMC.register.8=APMC_PCDR
group.APMC.register.10=APMC_PCSR
group.APMC.register.12=APMC_CGMR
group.APMC.register.14=APMC_PCR
group.APMC.register.16=APMC_PMR
group.APMC.register.18=APMC_SR
group.APMC.register.20=APMC_IER
group.APMC.register.22=APMC_IDR
group.APMC.register.24=APMC_IMR

##				APMC_SCER
APMC_SCER.width=32
APMC_SCER.access=memorymapped
APMC_SCER.address=APMC_BASE+0x00
APMC_SCER.byteEndian=little
APMC_SCER.type=bitfield

APMC_SCER.bits.0.name=Reserved
APMC_SCER.bits.0.range=1..31

APMC_SCER.bits.1.name=CPU
APMC_SCER.bits.1.range=0..0
APMC_SCER.bits.1.type=enum
APMC_SCER.bits.1.enum.0.name=ENABLE System Clock *** Write Only ***
APMC_SCER.bits.1.enum.1.name=Error: This register should always read zeros 

##				APMC_SCDR
APMC_SCDR.width=32
APMC_SCDR.access=memorymapped
APMC_SCDR.address=APMC_BASE+0x04
APMC_SCDR.byteEndian=little
APMC_SCDR.type=bitfield

APMC_SCDR.bits.0.name=Reserved
APMC_SCDR.bits.0.range=1..31